File:SNES power input and regulator circuit (Donaldson redraw).png
Summary
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Crop of the power section of Jonathon W. Donaldson's community redraw of the NTSC Super NES main board (SNS-CPU-GPM-01/02 and SNS-CPU-RGB-01/02), revision 1.5, 24 February 2014. From right to left: DC jack J1 ("+10V (Nominal) for NTSC"), line filter T1 (ZJVS5102-2P) with C30 and C31, fuse F1 1.5 A, diode D1 (PB1100), C67 1000 uF 25 V (drawn in brackets), C32, power switch P3, C33, surge absorber VA1 (ERZC050K220), C63 33 uF 25 V, regulator U12 7805 (pin 1 IN, pin 2 GND, pin 3 OUT) with C34 0.1 uF and C81 1 uF, and transistor Q18 (2SC2412) with R76 1.8 k and C64 33 uF 25 V feeding the VS rail. Not a Nintendo document.
Source
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Cropped from File:Snes schematic.pdf, described on SNES Schematic. Rendered at 600 dpi.
Author
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Jonathon W. Donaldson (redraw). The circuit is Nintendo's.
Licence
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No licence accompanies the drawing. Hosted for repair reference.
File history
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 10:46, 25 October 2026 | | 2,605 × 290 (74 KB) | Josh (talk | contribs) | Upload for SNES repair guide |
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File usage
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