File:Sega Saturn VA0 PAL PLL IC20 schematic.png
Summary
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The clock generator section of Sega's schematic for the VA0 PAL Saturn main board (main board sheet 3/6): IC20, the 315-5746 PLL, with crystal X1 (17.7344 MHz), the electrolytics CE18 to CE22, the chokes L3 and L5, the DOTSEL and NPSEL inputs, and the clock outputs buffered by IC23 and IC24 (74VHC04) to test points TP19 to TP21 and TP84 to TP86.
Source
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Sega Enterprises, Service Manual: Sega Saturn (PAL), No. 013-1, June 1995, section 8, schematic diagram 3, printed page 18 (PDF page 15), cropped. Hosted on this wiki as File:Sega service manual - sega saturn pal - no. 013-1 june 1995.pdf; see Sega Service Manual - Sega Saturn Pal - 1 June 1995.
Author
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Sega Enterprises, Ltd.
Licence
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Copyright Sega Enterprises, Ltd. Hosted for preservation and repair reference, with the source cited.
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 10:58, 25 October 2026 | | 1,815 × 1,396 (610 KB) | Josh (talk | contribs) | Upload for repair guide |
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