Sinclair ZX81 ULA
The Sinclair ZX81 ULA is the 40-pin uncommitted logic array, made by Ferranti, that does most of the work in the Sinclair ZX81 apart from the processor and memory. It generates the CPU clock and the non-maskable interrupt, shifts the display out as a three-level video and tape signal, reads the keyboard and the tape input, and decodes the ROM and RAM selects. Sinclair's kit instructions call it IC1, the "Sinclair Logic IC"; the circuit diagram calls it "Sinclair Computer Logic".[1] Ferranti's own files, released in the Ferranti Archives 2026, hold the logic diagrams of three ZX81 ULA types, 2C158, 2C184 and 2C210, the transistor-level drawing of the pin circuits, the Timex Sinclair 1000 specification for the same chip, and Ferranti's 1983 test notes on ULAs returned from Timex.
Board-level fault finding is in the Sinclair ZX81 Troubleshooting Guide.
Chip types and drawings
[edit | edit source]The logic diagrams carry the title block of Ferranti Electronics Limited, Ferranti Microelectronics Centre, Hollinwood, Oldham. Each is a single plotted sheet of the whole chip, gate by gate.[2][3][4]
| Type | Drawing | Job number | Issues and dates | Notes |
|---|---|---|---|---|
| 2C158 | Logic diagram LD6532/ULA2C158/1 | LD6532 | Issue 1 21 August 1980, 2 28 August, 3 16 September, 4 23 September, 5 26 September 1980 | The first ZX81 ULA. Five issues in five weeks[2] |
| 2C158 | Cell and pin-circuit drawing ULA 2C158/2 | – | Issue 4, 24 September 1980 | Transistor-level circuits of the flip-flop cells and every kind of pin. "2C210" is written by hand below the title block[5] |
| 2C184 | Logic diagram LD6532/ULA2C184/1 | LD6532 | Issue 1, 7 April 1981 | Same job number as the 2C158[3] |
| 2C210 | Logic diagram LD6679/ULA2C210/1 | LD6679 | Issue 1, 12 January 1982 | New job number[4] |
The pin allocation is the same on all three logic diagrams.[2][3][4] The functional blocks are also the same: the keyboard, USA/UK and TAPE IN inputs read onto the data bus through open-collector drivers; an eight-bit video shift register (Q1 to Q8) loaded from the data bus; a character-code latch that drives address lines A3 to A8; a three-bit line counter that drives A0 to A2; and an eight-stage horizontal counter with LINE-SYNC and FRAME-SYNC decoding.[3]
The differences visible from comparing the sheets, without a gate-by-gate check, are these:[2][3][4]
- 2C158 to 2C184: the clock into the first horizontal-counter stage (Q21) passes through two pairs of inverters on the 2C184 sheet, where the 2C158 sheet has a single inverter.
- 2C184 to 2C210: a chain of three inverters from the horizontal counter feeds an added four-input NOR gate beside the LINE-SYNC gate, and the video signal into the three-level output passes through an added gate and an inverter marked "R/2".
None of the sheets says why the changes were made. In the archive, the 2C210 drawing came from an unlabelled folder with the 2C158 drawings and the ZX Printer ULA logic, while a yellow wallet labelled "ULA 2C210 - ZX81" is catalogued as holding the 2C184 logic and two ZX Printer drawings.[6][7]
Pin-out
[edit | edit source]| Pin | Signal | Pin circuit (Ferranti drawings) | Pin | Signal | Pin circuit (Ferranti drawings) |
|---|---|---|---|---|---|
| 1 | A7 | Tri-state output | 21 | D6 | Open-collector output, 16K pull-up, input buffer |
| 2 | A8 | Tri-state output | 22 | USA/UK | Input, 16K pull-up |
| 3 | A2 | Tri-state output | 23 | D5 | As D6 |
| 4 | A1 | Tri-state output with an input path (bidirectional on the 2C158) | 24 | D4 | As D6 |
| 5 | A0 | As A1 | 25 | KB4 | Keyboard input, 16K pull-up, "3 VBE" emitter follower |
| 6 | /RD | Input | 26 | D3 | As D6 |
| 7 | /IORQ | Input | 27 | KB3 | As KB4 |
| 8 | /WR | Input | 28 | D2 | As D6 |
| 9 | /MREQ | Input | 29 | KB2 | As KB4 |
| 10 | /M1 | Input | 30 | D1 | As D6 |
| 11 | A14 | Input | 31 | KB1 | As KB4 |
| 12 | /RAM CS | Totem-pole output | 32 | D0 | As D6 |
| 13 | /ROM CS | Totem-pole output | 33 | KB0 | As KB4 |
| 14 | CPU clock (Φ) | Totem-pole output | 34 | GND | – |
| 15 | /NMI | Open-collector output, internal 5K pull-up | 35 | Ceramic resonator | Oscillator input |
| 16 | TV/TAPE | Three-level output | 36 | A3 | Tri-state output |
| 17 | /HALT | Input | 37 | A4 | Tri-state output |
| 18 | A15 | Input | 38 | A5 | Tri-state output |
| 19 | D7 | As D6 | 39 | A6 | Tri-state output |
| 20 | TAPE IN | Input, 400 Ω series resistor and clamp diodes | 40 | VCC | +5 V |
The pin numbers are from the three Ferranti logic diagrams and agree with Sinclair's ZX81 circuit diagram and with the pin designation in Timex's TS1000 specification.[3][1][8] The pin circuits are from the 2C158 cell drawing.[5]
Pin circuits
[edit | edit source]The 2C158 cell drawing labels the internal logic "CML" throughout, with a second internal supply, "Vs", alongside +VCC. Every pin passes through a cell that translates between the internal logic and the TTL-level pin.[5] A pencil sketch in the same Ferranti folder gives the internal rail as 0.9 V.[9] Timex's specification had described the chip as CMOS; Ferranti struck that out and wrote "bipolar".[8]
- The control inputs (/MREQ, /WR, /RD, /M1, /HALT, /IORQ, A14, A15) and USA/UK each enter through 5K into an emitter follower.[5] The logic diagrams draw 16K pull-ups to VCC on the data, keyboard, USA/UK and control inputs, and Ferranti's note on the Timex specification reads "16K pull up resistor on all TTL I/P except A0, A1".[3][8]
- The keyboard inputs KB0 to KB4 have a 16K pull-up and an emitter-follower input marked "3 VBE". Timex's specification lists them, with USA/UK, as "TTL inputs with higher threshold": 2.7 V minimum high and 1.0 V maximum low, against 2.0 V and 0.8 V for the ordinary TTL inputs.[5][8]
- The data bus pins D0 to D7 are bidirectional: an open-collector driver with a 16K pull-up, and an emitter-follower input.[5] Timex's specification gives a 5K pull-up for all the open-collector outputs, D0 to D7 included; Ferranti's drawings give 5K only on /NMI.[8][5]
- The address outputs A0 to A8 are tri-state. During display fetches the ULA drives A3 to A8 from its character latch and A0 to A2 from its line counter. On the 2C158, A0 and A1 also have an input path from the pin.[3][5]
- /ROM CS, /RAM CS and the clock are totem-pole outputs.[5]
- /NMI is an open-collector output with an internal 5K pull-up to VCC.[5]
- TV/TAPE (pin 16) is the three-level output. The inverted SYNC and VIDEO signals drive two transistors with 2K and 4.4K loads; an emitter follower with a 1K pull-down then feeds the pin through an internal 200 Ω resistor.[5][9]
- TAPE IN (pin 20) has clamp diodes to +5 V and to ground at the pin, a 400 Ω series resistor and 5K to the 0.9 V rail, before a transistor with a 16K collector load. The sketch shows a series capacitor ahead of the pin.[5][9] Ferranti noted on the Timex specification that this input has no hysteresis, with thresholds of 0.2 V maximum low and 1.0 V minimum high.[8]
- For the resonator on pin 35, the cell drawing shows the ceramic resonator reaching the oscillator through 100 pF. Timex's specification draws a 6.5 MHz resonator to ground, coupled through 100 pF, with 18 kΩ from the oscillator input to ground, and an output of 6.5 MHz.[5][8] On the ZX81 board these parts are X1 (a CDA 6.5 MHz three-lead ceramic filter), C6 (100 pF) and R4 (18 kΩ).[1]
Video levels at pin 16
[edit | edit source]| Level | Ferranti pencil sketch | Timex TS1000 specification |
|---|---|---|
| White | 4 V | 4.0 V typical |
| Black | 2.8 V | 3.0 V typical |
| Sync | 0 V | 0.1 V typical, 0.4 V maximum |
Both are factory figures for the chip, the first from Ferranti's undated sketch and the second from Timex's November 1982 specification, which Ferranti ticked.[9][8] Television magazine's 1986 servicing article, measuring a working machine, gives about 2 V from the peak to the bottom of the sync pulses at pin 16.[10] The sources do not say what load each figure assumes. On the factory figures, sync takes the pin to within 0.4 V of ground, so a pin 16 that never falls near 0 V points at the ULA's sync or at a fault loading the line.
Timex Sinclair 1000 logic array specification
[edit | edit source]Timex specification EG-M-507, "Logic array, TS-1000", revision A of 20 September 1982 and revision B of 22 November 1982, defines the chip for the Timex Sinclair 1000 (model M330) as the "I/O controller circuit". Ferranti's copy is marked up wherever Timex's assumptions did not fit the Ferranti part.[8] A Timex package drawing, 330-810851 revision C, names the approved vendor as Ferranti, part number 2C158, with 2C184E as the alternate.[11]
| Item | Timex's text | Ferranti's annotation or the Timex drawing |
|---|---|---|
| Technology | 40-pin CMOS device | "BIPOLAR" |
| Frame sync | Countdown chain for line and frame sync | "Frame sync is produced by µP and software, not ULA" |
| Oscillator | Ceramic oscillator (two pins) | "Only one pin" |
| Input pull-ups | – | "16K pull up resistor on all TTL I/P except A0, A1" |
| Output sink current | VOL 0.4 V at 2.5 mA | "With sink currents of only 2½ mA, operation might be too slow. Ours are 8 mA (16 mA)" |
| /RAM CS delay from /MREQ, 30 pF | Typed maximum blacked out | 56 ns maximum |
| /ROM CS delay from /MREQ, 30 pF | Typed maximum blacked out | 68 ns maximum |
| A0 to A8 delay from /M1, 30 pF | Typed maximum blacked out | 93 ns maximum |
| D0 to D7 from /IORQ, 50 pF | 400 ns maximum | Ticked |
| TAPE IN | Input with hysteresis (1.6 V and 0.8 V thresholds) | "There is no hysteresis on our I/P"; VIL 0.2 V maximum, VIH 1.0 V minimum |
| Package | – | 40-pin plastic DIL, body 52.58 mm long and 14.10 mm wide, 2.54 mm pitch |
Sources: the specification and the package drawing.[8][11] The specification also says the CPU reads USA/UK with the keyboard data to decide the TV system (50 or 60 Hz); the Ferranti drawings do not say which level selects which.[8][3]
ULA returns in 1983
[edit | edit source]Timex built the ZX81 for Sinclair at Dundee and the TS1000 at Timex Portugal. On 11 February 1983 Sinclair, Timex and Ferranti met over ULA rejects; the agenda lists 50 rejected 2C184 and 2C210 ULAs from ZX81 production at Dundee, TS1000 rejects from Portugal, TS1000 customer returns in the United States, and "ULA2C184/158 rescreened devices" held by Ferranti.[12]
Two days earlier Ferranti had written up its tests on the Timex USA and Timex Portugal returns. Each device was run on a Membrain tester at 5 V and swept from 4 to 6 V, on a GenRad tester, and in real ZX81s at Ferranti's MEC and GEM sites (the GEM machine was a test box, also used heated to 70 °C) and in a Timex US machine.[13]
| Batch | Category | Devices |
|---|---|---|
| Timex USA, 17 devices (2C184 and 2C210) | Good: pass everything | 4 |
| Good except in the US ZX81; passes in the GEM ZX81 at 70 °C | 1 | |
| Passes the testers but fails in a ZX81 when warm | 1 | |
| Marginal on test and fails in a ZX81 when warm | 2 | |
| Blown up by overvoltage | 3 | |
| Passes production test but does not work in ZX81s | 4 | |
| Probably never worked properly | 2 | |
| Timex Portugal, 9 devices | Blown up ("by them", the sheet says); damage noted at pin 19 on one and pin 10 on the other | 2 |
| Possibly blown up: one with pin 20 (tape input) working poorly, one with pin 24 stuck high | 2 | |
| Temperature failure (good cold) | 1 | |
| Assembly failure, never worked | 1 | |
| Faulty logic or faulty sync, probably never worked | 2 | |
| Good after repairing a broken pin | 1 |
Source: Ferranti's handwritten results.[13] The Portugal sheet describes its devices as "the 9 'MEC failures' from the sample of 20 out of 315 from 24K units". In the Membrain supply sweep some devices failed only at one end, recorded as "F >4.9V", "F >5.5V" or "FAIL <4.6V".[13]
What these 1983 samples suggest for a repair today (reasoning from a small sample, not a rule):
- Three of the 17 US returns were blown up by overvoltage, and two of the nine Portugal devices were blown up, with two more possibly so. Before fitting a replacement ULA, find out why the first one died: check the adaptor, the 7805 regulator and the +5 V rail, because a fault that destroyed one ULA can destroy the next.
- Several ULAs passed every factory tester and failed only in a ZX81, or only when warm. A ZX81 that fails after warming up can have a marginal ULA, and a ULA that works in one machine is not proven good in another; substitution in the machine with the fault is the practical test.
- Pin 20 is the tape input and pin 24 is D4. The Portugal sheet shows that a damaged ULA can fail on a single pin while the rest works.
Identification
[edit | edit source]- Sinclair's 1981 kit component list gives IC1 as "Sinclair Logic IC, 40 pins, 158 printed underside", which matches Ferranti's type number 2C158.[1]
- The board photograph in Sinclair's ZX81 manual shows the logic chip with a paper label, "Sinclair Computer Logic", beside an NEC D780C-1 processor and a ROM labelled "(c) 1980 Sinclair Research Ltd".[14]
- Timex's package drawing names Ferranti 2C158 as the approved part and 2C184E as the alternate. Timex-built ZX81 and TS1000 machines in early 1983 had 2C184 and 2C210 ULAs among their rejects.[11][12][13]
- None of the Ferranti drawings shows a production marking or explains the letter suffix. Production chips are marked on top, for example "FERRANTI ULA 2C210E" on the Issue 3 board below.
All three types have the same pin allocation on Ferranti's drawings, so they are pin-compatible on paper.[2][3][4] The drawings do not say whether every ZX81 board issue accepts every type, and Timex approved only the 2C158 and the 2C184E for the TS1000.[11]
Probing the ULA
[edit | edit source]The pins worth checking first on a dead or blank ZX81, with what the Ferranti drawings show behind them:[3][5]
| Pin | Signal | Notes |
|---|---|---|
| 40, 34 | +5 V, ground | Supply to the ULA |
| 35 | Ceramic resonator | The ULA derives the clock from it |
| 14 | CPU clock | Totem-pole output; on the ZX81 it reaches the Z80 through the TR2 buffer[10] |
| 16 | TV/TAPE | Three-level output; see Video levels at pin 16 |
| 15 | /NMI | Open collector with its own 5K pull-up |
| 12, 13 | /RAM CS, /ROM CS | Totem-pole outputs |
| 33, 31, 29, 27, 25 | KB0 to KB4 | 16K pull-up inside the ULA; the Television logic-probe readings show all five high at the cursor[10] |
Television magazine's logic-probe readings for every ULA pin at the inverse K cursor, and the rest of the fault-finding sequence, are in the Sinclair ZX81 Troubleshooting Guide.[10]
Documents
[edit | edit source]Ferranti Archives 2026 scans cited above:
- ZX81-FER-SCH-105: 2C158 logic diagram, issue 5.
- ZX81-FER-SCH-103: 2C158 cell and pin circuits.
- ZX81-FER-SCH-011: 2C184 logic diagram.
- ZX81-FER-SCH-102: 2C210 logic diagram.
- ZX81-FER-NOT-104: pencil sketch of pins 20 and 16 with video levels.
- TS1000-TMX-SPC-096 and SPEC-TMX-DRW-095: Timex specification and package drawing.
- SPEC-FER-REP-060 and SPEC-UNK-AGN-061: 1983 returns and meeting agenda.
The whole collection is described at Ferranti Archives 2026. The Sinclair ZX Spectrum ULA page covers Ferranti's later Spectrum chips.
Related pages
[edit | edit source]- Sinclair ZX81
- Sinclair ZX81 Troubleshooting Guide
- Sinclair ZX81 General Maintenance
- Sinclair ZX81 Assembly Instructions
- Sinclair ZX Printer
- Sinclair ZX Spectrum ULA
References
[edit | edit source]- ↑ 1.0 1.1 1.2 1.3 Sinclair Research, ZX81 Assembly Instructions (1981), with circuit diagram SRC 049 and the Issue One layout, Ferranti Archives 2026 (ZX81-SIN-LIT-131); the same edition as the copy described at Sinclair ZX81 Assembly Instructions. Source for "Sinclair Logic IC, 40 pins, 158 printed underside", the ULA pin numbers on the circuit diagram, and X1, C6 and R4.
- ↑ 2.0 2.1 2.2 2.3 2.4 Ferranti logic diagram LD6532/ULA2C158/1 for the ZX81 ULA 2C158, issues 1 to 5 (21 August to 26 September 1980), Ferranti Archives 2026 (ZX81-FER-SCH-105). Source for the 2C158 issue dates, its job number and its pin allocation.
- ↑ 3.00 3.01 3.02 3.03 3.04 3.05 3.06 3.07 3.08 3.09 3.10 Ferranti logic diagram LD6532/ULA2C184/1 for the ZX81 ULA 2C184, issue 1, 7 April 1981, Ferranti Archives 2026 (ZX81-FER-SCH-011). Source for the 2C184 drawing, the pin list with 16K pull-ups, the functional blocks, and the 2C158 to 2C184 counter-clock change on comparison with the 2C158 sheet.
- ↑ 4.0 4.1 4.2 4.3 4.4 Ferranti logic diagram LD6679/ULA2C210/1 for the ZX81 ULA 2C210, issue 1, 12 January 1982, Ferranti Archives 2026 (ZX81-FER-SCH-102). Source for the 2C210 drawing, its job number, its pin list and the gating added at the LINE-SYNC decode and in the video path.
- ↑ 5.00 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 5.09 5.10 5.11 5.12 5.13 Ferranti cell and pin-circuit drawing ULA 2C158/2, issue 4, 24 September 1980, Ferranti Archives 2026 (ZX81-FER-SCH-103). Source for the CML internal logic and Vs rail, the input, keyboard, data-bus, address, chip-select, clock, /NMI, TV/TAPE, TAPE IN and oscillator cells, and the bidirectional A0 and A1.
- ↑ Unlabelled Ferranti folder that held the 2C210 and 2C158 drawings, the pencil sketch and the ZX Printer ULA logic, Ferranti Archives 2026 (GEN-FER-FOL-107).
- ↑ Ferranti wallet folder labelled "ULA 2C210 - ZX81", Ferranti Archives 2026 (ZX81-FER-FOL-013). The archive catalogue places the 2C184 logic and two ZX Printer drawings in it.
- ↑ 8.00 8.01 8.02 8.03 8.04 8.05 8.06 8.07 8.08 8.09 8.10 Timex product engineering specification EG-M-507 revision B, "Logic array, TS-1000", 22 November 1982, with Ferranti's annotations, Ferranti Archives 2026 (TS1000-TMX-SPC-096). Source for "bipolar", frame sync from the processor and software, the input thresholds, the 2.5 mA against 8 mA (16 mA) sink current, the delay maxima, the TAPE IN thresholds, the 6.5 MHz resonator circuit, the tri-level output levels and the pin designation.
- ↑ 9.0 9.1 9.2 9.3 Undated pencil sketch headed "ZX81." of the ULA's TAPE IN (pin 20) and TV/TAPE (pin 16) circuits, Ferranti Archives 2026 (ZX81-FER-NOT-104). Source for the 0.9 V internal rail and the levels at pin 16: white 4 V, black 2.8 V, sync 0 V.
- ↑ 10.0 10.1 10.2 10.3 "Servicing Sinclair Computers, Part 2", Television magazine, 1986. Transcribed at https://k1.spdns.de/Vintage/Sinclair/82/Sinclair%20ZX%20Spectrum/Repair/rep2%20-%20the%20ZX81.html (retrieved 2026-10-01). Source for about 2 V peak to sync bottom at pin 16, the TR2 clock buffer and the logic-probe readings.
- ↑ 11.0 11.1 11.2 11.3 Timex package drawing 330-810851 revision C, "IC package, ULA", stamped 17 November 1982, Ferranti Archives 2026 (SPEC-TMX-DRW-095). Source for Ferranti 2C158 as the approved part with 2C184E as the alternate, and the package dimensions.
- ↑ 12.0 12.1 Agenda for the Sinclair, Timex and Ferranti meeting of 11 February 1983, with handwritten notes, Ferranti Archives 2026 (SPEC-UNK-AGN-061). Source for the 50 ZX81 rejects at Dundee, the TS1000 rejects and returns, and the rescreened 2C184/158 devices.
- ↑ 13.0 13.1 13.2 13.3 Ferranti handwritten test results for ZX81 ULAs 2C184 and 2C210 returned by Timex USA and Timex Portugal, 9 February 1983, Ferranti Archives 2026 (SPEC-FER-REP-060). Source for the test stations, the return categories and counts, the pin-level findings and the supply-sweep failures.
- ↑ Page 162 of Sinclair's ZX81 manual, Sinclair ZX81 BASIC Programming, chapter 25, with a labelled board photograph, Ferranti Archives 2026 (ZX81-UNK-LIT-138). Source for the "Sinclair Computer Logic" label.