Sinclair ZX Spectrum 128 ULA

The 7K010 pinning arrangement (top view) from Ferranti's specification, issue 4, April 1986.

The Sinclair ZX Spectrum 128 ULA is the custom chip at the centre of the Sinclair ZX Spectrum 128. It generates the picture and its sync, controls the contended RAM and the ROM chip select, stops the Z80's clock when the display needs the memory, reads the keyboard and the tape input, and drives the MIC and beeper output. Ferranti made it as type 7K010, which its specification describes as a customised CML array titled "Video Display Generator", in a 48-pin plastic DIL package. Sinclair's service manual lists it as IC1, "7C001", made by Ferranti, in a 48-way DIL socket, Sinclair's own logic drawing labels it "7C ULA", and the production parts Ferranti examined in November 1985 were marked "ULA7K010E5". The grey Sinclair ZX Spectrum +2 uses the same part (see below).

The main sources are Ferranti's working files on the chip, now part of the Ferranti Archives 2026: the pinout agreed with Sinclair in June 1985, the logic drawings, the device specification, and the notes and memo on parts that Sinclair returned in late 1985. These are factory documents from 1985 and 1986. The faults they describe were found on early production parts and led to changes in Ferranti's tests; they help a repairer recognise a failing ULA, but they are not a claim that every 128 has them.

7K010 at a glance

Item	Value
Ferranti type	7K010; package mark ULA7K010E5 on the parts Ferranti examined in 1985
Other names	7C001 (Sinclair parts list); "7C ULA" (Sinclair drawing); "7K010-5" (Sinclair telex) and "Mk5" (Ferranti memo) for the 1985 production parts
Technology	Customised CML array
Package	48-pin plastic DIL; fitted in a 48-way DIL socket on the 128
Supplies	VCC1 5 V ±5 % on pin 14; VCC2 2 V (nominal) on pin 13; ground on pin 48
Typical supply current	45 mA (VCC1), 85 mA (VCC2)
Clock input	17.7345 MHz on pin 1
Operating temperature	0 to 50 °C
Used in	Sinclair ZX Spectrum 128 (IC1); grey Sinclair ZX Spectrum +2 (IC14)

Development

Project Derby, June 1985

To Ferranti the 128 was "Project Derby". A telex-style message of 14 June 1985, headed "Pinning arrangement for ULA7K010 Project Derby", confirms to Sinclair Research the pinout already given over the telephone. In the typed list pin 46 is a 4.43 MHz output; it has been struck through in blue pen with "8MHz" written beside it. In the April 1986 specification pin 46 is N8.86MHz, the inverse of the 8.86 MHz output on pin 47; every other pin is as in the June message.

Drawings and specification issues

7K010 document issues in the Ferranti files

Date	Document	Issue
7 June 1985	Top-level diagram, drawing "ULA 7K010"	Issue 1
11 and 20 June 1985	Sheet 2: flip-flop and comparator macros, drawing LD6790/ULA 7K010/2	Issues 1 and 2
14 June 1985	Pinning confirmed to Sinclair (Project Derby)	–
20 June 1985	Sheet 5: MIC/LS output and EAR input circuits, drawing 7K010/5	Issue 1
24 June 1985	D.C. and A.C. specification	Issue 1
4 September 1985	Top-level diagram	Issue 2
26 September 1985	D.C. and A.C. specification	Issue 2
17 October 1985	D.C. and A.C. specification	Issue 3
9 April 1986	D.C. and A.C. specification	Issue 4
16 May 1986	Top-level diagram	Issue 3

Ferranti's pencil notes on output loading assume eight 4164 DRAMs (10 µA and 7 pF each) on every address and strobe output, a 470 Ω series resistor on the address lines and NRAS, and a 680 Ω series resistor on the ROM chip select. The specification rates exactly those pins (NROMCS, NCAS, NDRAMWE, NRAS and A0 to A7) to sink 16 mA, and a pencil note on the printout lists the same pins under "16mA test". Sinclair's logic drawing has the same arrangement: the contended bank IC6 to IC13 hangs directly on the ULA's address and strobe pins, and ROMCS reaches the ROM through R33, 680 Ω.

Pinout

The pin numbers below are the same in the June 1985 telex, the April 1986 specification, Ferranti's pin tables and the Sinclair and Timex board drawings. The "stage" column gives the input or output type from the specification and, after the semicolon, the cell label on the top-level diagram. Sinclair's drawings use the names in the last column; the Timex production drawing labels pins 32, 30, 29, 26 and 25 as KB0 to KB4, the reverse of Ferranti's names, with the same wiring.

7K010 pin functions

Pin	Ferranti name	Stage	Function on the 128	Sinclair drawing
1	CK	17 MHz clock input	17.7345 MHz master clock from the IC37 74S04 oscillator	17M
2	NCAS	Output, R34 fast totem pole; R34	CAS for the contended RAM, IC6 to IC13	CASL
3	C	Output, R34 fast totem pole; R34	Output used in Ferranti's speed tests, which measured from the clock input to this pin	C
4	A0	Output, R36 fast tristate, and emitter-follower input; R36 and EF4	Multiplexed row and column address to the contended RAM	DMA0
5 to 10	A1 to A6	Output, R36 fast tristate; R36	Multiplexed row and column address to the contended RAM	DMA1 to DMA6
11	A7	Output, R36 fast tristate; R36	Address bit 7 to the contended RAM; selects screen page 5 or 7 from VB	DMA7
12	VB	Emitter follower with 18K pull-up; EF1	Video bank bit from the bank register IC31	VB
13	VCC2	Supply	2 V nominal; fed from +5 V through R34	VCC2
14	VCC1	Supply	5 V	VCC1
15	NRD	Emitter follower with 18K pull-up; EF1	Z80 /RD	RDL
16	NWR	Emitter follower with 18K pull-up; EF1	Z80 /WR	WRL
17	NINT	Resistive pull-up (5K2); R40	Z80 interrupt, once every 20 ms	INTL
18	NDRAMWE	Output, R34 fast totem pole; R34	Write enable for the contended RAM	DRAMWEL
19 to 22	BLUE, GREEN, RED, BRIGHT	Output, R34 fast totem pole; R34	Digital colour and bright to the TEA2000 encoder and the RGB socket	B, G, R, BRIGHT
23	NSYNC	Output, R34 fast totem pole; R34	Composite sync	SYNC
24, 27, 28, 31, 33, 37	D0, D1, D2, D3, D4, D6	Emitter-follower input with R38 open-collector output; EF1 and R38	Data bus; keyboard rows are read on D0 to D4 and EAR on D6	D0 to D4, D6
36, 38	D5, D7	Emitter follower with 18K pull-up; EF2 and EF1	Data bus	D5, D7
25, 26, 29, 30, 32	KB0 to KB4	"3Vbe" emitter follower with 18K pull-up; EF3 (KB0 is also an open-collector output)	Keyboard rows from the membrane's 5-way tail, each with a pull-up resistor on the board (R65 to R69)	KB0 to KB4
34	EAR	Schmitt trigger	Tape input	EAR
35	NMIC/LS	Three-level special output; "MIC/LS special peripheral"	MIC socket and beeper sound	MIC
39	NCPU	Resistive pull-up (2K1); RP1	Z80 clock, 3.5469 MHz, stopped by the ULA during contention; buffered by TR3	PHICPU
40	NIORQ	Emitter follower with 18K pull-up; EF1	Z80 /IORQ, gated with A0 through TR6 on the 128	IORQL
41	NROMCS	Output, R34 fast totem pole; R34	ROM chip select, through R33 (680 Ω)	ROMCSL
42	NRAS	Output, R36 fast tristate; RTL2 stage then R36	RAS for the contended RAM	RASL
43, 44	A14, A15	Emitter follower with 18K pull-up; EF1	On the 128 these come from the paging PAL IC29 (its ULA14 and ULA15 outputs)	A14, A15
45	NMREQ	Emitter follower with 18K pull-up; EF1	Z80 /MREQ	MREQL
46, 47	N8.86MHz, 8.86MHz	8 MHz differential outputs	Colour subcarrier reference to the TEA2000 (IC36) XTAL inputs	8.8MHz-bar, 8.8MHz (analogue sheet)
48	GND	Supply	Ground	GND

Ferranti's specification marks A0, KB0, D0, D1, D2, D3, D4 and D6 as input/output pins.

Electrical characteristics

Supplies

The specification gives VCC1 as 5 V ±5 % on pin 14 and VCC2 as 2 V nominal on pin 13. On the 128, pin 13 is fed from the +5 V rail through R34, 15 Ω 0.5 W, with C30 (22 nF) at the pin and C75 (100 nF) on VCC1. Sinclair's parts list gives R34 as 15 Ω, 0.5 W or 1 W. The documents give no test voltage for pin 13 on a working board.

Supply currents (specification issue 4)

Parameter	Pin	Condition	Min	Typ	Max	Note
ICC1	VCC1 (14)	VCC1 = 5 V	37.5 mA	45 mA	67.5 mA	Test limit +15 mA because of the external 560 Ω pull-downs on pins 46 and 47
ICC2	VCC2 (13)	VCC2 = 2 V	71 mA	85 mA	127.5 mA

The 560 Ω pull-downs are in the test conditions; on Sinclair's analogue drawing pins 46 and 47 have 1.5 kΩ (R90, R100) to ground.

D.C. limits

D.C. characteristics at VCC1 = 5 V (specification issue 4)

Parameter	Pins	Condition	Limit
VIL max	KB0 to KB4		1.4 V
VIL max	All inputs except KB0 to KB4 and EAR		0.8 V
VIH min	KB0 to KB4		2.8 V
VIH min	All inputs except KB0 to KB4 and EAR		2.0 V
VT− typ	EAR		0.7 V
VT+ typ	EAR		0.85 V
IIL max	KB0 to KB4	VIN = 0 V	−0.5 mA
IIL max	NMREQ, NWR, NRD, NIORQ, A14, A15, VB, D5, D7	VIN = 0 V	−1.0 mA
IIL max	CLOCK	VIN = 0 V	−0.9 mA
IIL max	EAR	VIN = 0 V	−10 µA
IIH max	KB0 to KB4	VIN = 5 V	+100 µA
IIH max	NMREQ, NWR, NRD, NIORQ, A14, A15, VB, D5, D7	VIN = 5 V	+1.0 mA
IIH max	CLOCK	VIN = 5 V	+20 µA
IIH max	EAR	VIN = 1 V	+500 µA
VOL max	NROMCS, A0 to A7, NRAS, NCAS, NDRAMWE	Isink 16 mA	0.5 V
VOL max	RED, GREEN, BLUE, BRIGHT, NINT, NSYNC, D0 to D4, D6, C	Isink 8 mA	0.5 V
VOL max	NCPU	Isink 1 mA	0.3 V
VOH min	NROMCS, A0 to A7, NRAS, NCAS, NDRAMWE	Iout 400 µA	2.4 V
VOH min	RED, GREEN, BLUE, BRIGHT, NINT, NSYNC, D0 to D4, D6, C	Iout 200 µA	2.4 V
VOH min	NCPU	Iout 1 mA	1.0 V
Ioff	NRAS, A0 to A7	Vout 0 V / 5 V	−20 µA / +20 µA
V(swing)	8.86MHz, N8.86MHz	V(high) − V(low)	0.4 V min, 0.7 V max
Mean D.C. level	8.86MHz, N8.86MHz	(V(high) + V(low)) / 2	3.6 V typ

The NMIC/LS pin has three output levels set by two internal signals, MIC and NLS:

NMIC/LS output (pin 35)

MIC	NLS	Output
High	High	0.5 V max
Low	Low	3.5 V min
High	Low	3.5 V min
Low	High	0.65 V min, 0.85 V max

Sinclair's service manual explains why: when saving, the MIC level is only just enough to modulate the 128's TV sound carrier, but during BEEP the CPU writes to bit 4 of port 254 instead, which raises the output so that the tone is clearly heard.

Clock (A.C. specification)

The clock waveform at pin 1 is specified at 17.7345 MHz, a period (Tp) of 56.39 ns, measured at VIN = 1.4 V with VCC1 = 5 V and VCC2 = 2 V. The high time must be at least 0.48 Tp at 50 °C and 0.45 Tp at 25 °C; the low time at least 0.46 Tp at 50 °C (the 25 °C figure is not clearly legible on either copy).

Internal structure

The clock input and the start of the divider chain on Ferranti's top-level diagram, issue 2. Pin 1 is buffered twice: one branch drives the toggle flip-flop that feeds pins 46 and 47, the other the "÷2.5" stage that clocks the "÷456 sync counter".

Ferranti's top-level diagram draws the whole chip as gates and flip-flops with pin cells round the edge. Sheet 2 of the drawing set shows that the flip-flops (toggle, D-type and enabled types, some with synchronous reset) and the equality comparator are themselves built from NOR gates. Gates on the diagram carry cell labels such as R/2 and R/3; in Ferranti's data pages for its 5C and 6C ULA arrays these labels denote gates with double and treble current sources, which switch faster.

Clock and timing chain

The clock on pin 1 is buffered twice. One branch drives a toggle flip-flop whose output feeds a pair of buffers giving complementary outputs on pins 46 and 47, so those pins carry half the clock frequency (8.86 MHz). The other branch drives a "differential ÷2.5" stage (MOD 1), which clocks a "÷456 sync counter" (MOD 2) and, after it, a "÷311 sync counter" (MOD 3). On those labels, 17.7345 MHz ÷ 2.5 gives a 7.09 MHz count rate, 456 counts make a 64.3 µs line and 311 lines make a field of about 20 ms, which matches the 20 ms interrupt in Sinclair's manual. Decodes from the counters are labelled BLANK, N.SYNC, N.FIELD, VIDEN, LINE and N.INT.

Colour subcarrier

The TEA2000's published application circuit has its own crystal on pins 12 and 13; on the 128 the ULA's 8.8 MHz pair drives those pins instead, and the encoder derives its 4.43 MHz chroma carriers from it. Sinclair's manual notes that because the pixel clock and the colour carrier come from the same crystal, dot crawl is eliminated. On the board the pair reaches the TEA2000's XTAL1 and XTAL2 pins through C118 and C119 (1 nF) and R99 and R104 (470 Ω), with R90 and R100 (1.5 kΩ) to ground.

Memory control and contention

Signals labelled RASEXT, RASINT, NRAS ENABLE, CASEXT, CASINT, ADSEL, ADEN, NVIDEN and N.VIDACC generate the RAS, CAS and write-enable strobes for the contended RAM and switch the address pins between the display counters and the CPU's address. When the display is about to use the contended RAM and the CPU also addresses it, the ULA inhibits the CPU clock until its own access is finished. On the diagram this is a gate labelled "INHIBIT ØSTOP".

Display data path

Rows of data latches (labelled D, A and B latches), an eight-stage shift register and an attribute latch feed a colour selector that drives BLUE, RED, GREEN and BRIGHT through R34 output cells. The address bit A7 is driven from a gate combining VB with an internal signal; Sinclair's manual gives DMA7 as high at row time for both screen pages and equal to VB at column time, selecting page 5 or page 7.

Keyboard

Each KB input feeds a gate that drives an open-collector data output, putting the keyboard rows onto D0 to D4 when the CPU reads port 254.

EAR and MIC/LS cells

Sheet 5 gives these two pin cells at transistor level. The EAR input passes through 4.1 kΩ into a three-transistor Schmitt comparator whose output drives the internal logic; the MIC/LS output is an emitter follower switched by two transistors, one driven by MIC and one by LS-bar. The specification gives the EAR thresholds as 0.7 V and 0.85 V typical.

Production problems, autumn 1985

The production parts discussed in late 1985 are called "7K010-5" by Sinclair, "Mk5" by Ferranti's memo, and are marked "ULA7K010E5" on the package.

The Sinclair returns

Sinclair returned 19 devices with date codes 8536 and 8540 (weeks 36 and 40 of 1985). All 19 had passed Ferranti's production test. Ferranti's memo of 5 December 1985 summarises what was found:

7K010 Mk5 returns, December 1985 memo

Devices	Failure	Cause and Ferranti's action
7	A.C. performance (speed)	Devices whose on-chip resistors were more than 20 % above nominal failed on speed: 4 were between +20 % and +30 %, 3 above +30 %. IIL (min) and ICC (min) tests were added to production test at once; they remove the parts above +30 % but not those between +20 % and +30 %.
3	Wrong border colours	Functional failures. The test program was improved to reject them and an "Issue 2 probe program" was released.
3	8 MHz outputs	Tightening the D.C. limits removed two. The third needed a program change, to go into "Issue 2 Vanwell" in week 50, with the new functional tests.
6	No fault found	Ferranti asked Sinclair to send them back to pinpoint the faults.

Ferranti also television-tested 36 "bin 1" parts (date codes 8541 and 8543) taken from its Gem Mill stock. Two failed, and both could only have been rejected by a TV test. On one, the 8 MHz outputs worked at 1 MHz but not at 8 MHz, and it "blew up" after power had been applied for a few minutes during a speed test; the other gave a picture like returned device A. The memo asks whether rejecting parts with resistors more than 20 % above nominal is acceptable and whether a production TV test is needed, and asks for tubes from every batch to be TV-tested until that is known. The archive does not record the answer.

The resistor-tolerance speed problem

Ferranti's working notes of 11 November 1985 show the mechanism. For each part the engineer logged ICC1, ICC2 and the measured value of an on-chip resistor of nominal 5.2 kΩ, and plotted them: the higher the resistor value, the lower the supply current. A second graph plots each part's maximum operating frequency, measured from the clock input to the C output after a one-minute warm-up, against total supply current: about 19 MHz at 107 to 110 mA, rising to 22 to 25 MHz at 145 to 165 mA. Several parts failed only after warming up, and one, device I, measured 19.5 MHz and then 18.9 MHz after an hour. The chip's working clock is 17.7345 MHz.

From the failed parts the notes propose screening limits of ICC1 (min) 55 mA, ICC2 (min) 65 mA and a maximum resistor value of 6.75 kΩ (+30 %).

Sinclair's change requests

On 12 November 1985 Sinclair sent Ferranti a telex asking for two changes to the 7K010-5 ULA:

1. "Increase the overlap between D and E at the inhibit CLK stopping gate to remove the glitch on CLK at high temperatures."
2. "Bring P out on A7 during RAS rather than on A0 during CAS. This provides a 8 bit refresh which gives greater choice of RAM chip." It adds: "VCC should be brought out on A0 during CAS, VB should still be brought out on A7 during CAS."

It asked how soon samples could be made available and the lead time to 20K components.

Issue 3 of the top-level diagram, dated 16 May 1986, differs from issue 2 in two places. At the "INHIBIT ØSTOP" gate, issue 2 draws a capacitor to ground on its second input; issue 3 does not, and that input comes straight from the line above. Beside the NVIDEN gate, issue 3 adds two inverters in series on a line that runs straight through on issue 2. The drawing carries no revision notes, so it does not say which request, if either, these changes answer. The signal labels do not show whether the refresh change was made. Sinclair's service manual still asks for 4164s with 128-row refresh and describes DMA7 as above.

Timex's provisional production drawing of March 1986 has the CPU clock pull-up R73 (1 kΩ) and C129 (100 pF, at the base of the clock buffer TR3) circled and marked "removed" in another hand. Sinclair's service manual parts list still includes R73 (1 kΩ) and C129 (100 pF), so boards may differ here.

Failure symptoms seen by Ferranti

Ferranti's sketches of the picture from returned ULA7K010E5 parts 6 to 10, November 1985.

Ferranti's notes and memo record how each returned part behaved in a test machine. These are the symptoms of a failing 7K010 as seen by its maker:

Symptoms of returned 7K010 E5 parts

Symptom	Ferranti's note
No reset at power-up	Seen on several parts, some with a picture of bands or a grid, one with a blank picture and no colour
Resets, but vertical bars appear in the border after the first key press
Picture and sound correct, then a crash after a short time or about a minute	These parts failed the frequency test after warm-up
Noise over the picture, failing after a few seconds	"Clock failure (counter chain)"
Wavy vertical lines	Same as the counter-chain failure
Border command gives wrong colours	Functional failure, later caught by the improved test program
Horizontal black and white bands across the picture
Picture continually flashing, black and white lines between each colour
Colours correct but some lines and characters black, random squares of colour
Vertical lines with colour noise	"8.8 MHz divider (one output) dead"
Blank or white picture, no colour, no reset
Vertical lines in the picture, noise in the border

Among the parts that failed on the 8 MHz outputs, one had the diode clamp missing from one 8.8 MHz output.

On Ferranti's bench the speed-marginal parts failed only when warm.

Checking the ULA on a 128

The 128's ULA is socketed, so substituting a known good part is the definitive test. Before that:

1. Check +5 V at pin 14 and that pin 13 is fed through R34 (15 Ω); check ground on pin 48.
2. Check the 17.7345 MHz clock at pin 1. Sinclair's check point is IC37 pin 6, 17.73447 MHz with no jitter. The specification asks for a high time of at least 0.45 to 0.48 of the period.
3. Check the 8.8 MHz pair on pins 46 and 47. The specified swing is only 0.4 to 0.7 V about a mean of about 3.6 V, so expect a small signal, not a logic-level square wave.
4. Check the CPU clock at pin 39 and, after TR3, at the Z80 (IC2 pin 6, 3.54689 MHz). The ULA's output is a resistive pull-up specified at only 1.0 V minimum high at 1 mA; TR3 brings it up to a 5 V swing for the Z80.
5. Check RAS and CAS to the contended RAM (IC6 to IC13) after a reset, as in Sinclair's initialisation checks.

The Sinclair ZX Spectrum 128 Troubleshooting Guide covers the board around the ULA.

In the Spectrum +2

Amstrad's Spectrum +2 Service Manual lists IC14 as "ULA7K010E5/AMS40056", Amstrad part 172046, so the grey +2 uses the same Ferranti 7K010 or an Amstrad 40056 in its place. Its circuit diagram shows the same pin assignments. The +2 has no 17.7 MHz crystal: X1 is 35.4690 MHz, and a 74F74 flip-flop (IC13) divides it by two to give the "17M" clock on ULA pin 1. Spectrum for Everyone reports that some late 128 Version 6U boards also have a soldered Amstrad 40056 in place of the Ferranti 7K010E-5.

Documents in the Ferranti Archives

Ferranti kept the 7K010 papers in two wallets, labelled "Spectrum 128K" and "7K010 drawings".

• SPEC128-FER-FAX-030: pinning telex for Project Derby, 14 June 1985
• SPEC128-FER-SCH-083: drawing sheet 2, flip-flop and comparator macros, 20 June 1985
• SPEC128-FER-SCH-085: drawing sheet 5, MIC/LS output and EAR input cells, 20 June 1985
• SPEC128-FER-SCH-022: top-level diagram, issue 2, 4 September 1985
• SPEC128-FER-SCH-084: top-level diagram, issue 3, 16 May 1986
• SPEC128-FER-DAT-028 and SPEC128-FER-DAT-086: D.C. and A.C. specification, issue 4, 9 April 1986
• SPEC128-FER-NOT-029 and SPEC128-FER-NOT-032: pencil notes on output loads and the pin table by test pod
• SPEC128-FER-REP-035: working notes on the returned E5 parts, 11 November 1985
• SPEC128-FER-MEM-031: memo summarising the Mk5 returns, 5 December 1985
• SPEC128-SIN-FAX-034: Sinclair's change-request telex, 12 November 1985
• SPEC128-FER-POL-036: undated Polaroid of oscilloscope traces of RAS and CAS on a 7K010E5
• SPEC128-SIN-SCH-021, SPEC128-SIN-SCH-023, SPEC128-TMX-SCH-026 and SPEC128-TMX-SCH-027: the Sinclair and Timex board drawings, listed on the Sinclair ZX Spectrum 128 Service Manual page

Related pages

• Sinclair ZX Spectrum 128
• Sinclair ZX Spectrum 128 Troubleshooting Guide
• Sinclair ZX Spectrum 128 Service Manual
• Sinclair ZX Spectrum +2
• Sinclair ZX Spectrum ULA, the 48K machine's Ferranti ULA
• Sinclair ZX Spectrum Memory Timing
• Ferranti Archives 2026