Sinclair ZX Spectrum ULA
 | |
| Ferranti's pinning drawing for the first Spectrum ULA, type 5C102, issue 1, 21 December 1981 | |
| Specifications | |
|---|---|
| Manufacturer | Ferranti Electronics Limited, Chadderton and Hollinwood, Oldham |
| Type | Uncommitted logic array (current-mode logic), "video display generator" |
| Introduced | 5C102 specification issue 1, 14 December 1981 |
| Clock rate | 14 MHz crystal on pin 39; 3.5 MHz CPU clock out on pin 32 |
| Transistors / gates | 5C000 array of 440 cells (5C102, 5C112); 6C000 array of 528 cells (6C001) |
| Package | 40-pin plastic DIL |
| Voltage | Vcc1 +5 V ±5% (pin 14); Vcc2 2 V nominal (pin 13) |
| Used in | Sinclair ZX Spectrum 16K and 48K, Sinclair ZX Spectrum+ |
| Part number | 5C102, 5C112, 5C114, 6C001 (marks 3 to 7), 6C011 |
The Sinclair ZX Spectrum ULA (IC1 on the main board) is the Ferranti uncommitted logic array that does most of the work in the 16K and 48K Sinclair ZX Spectrum apart from the Z80A processor, the ROM and the RAM. It generates the TV picture from display memory, shares the lower 16K of RAM with the CPU by stopping the CPU clock when both want it, reads the keyboard and the EAR input, drives the loudspeaker and the MIC output, and divides its 14 MHz crystal down to the 3.5 MHz CPU clock.[1][2] Ferranti made it in several types and marks between late 1981 and 1984: the 5C102 and 5C112 on the 440-cell 5C000 array, the 5C114, the 6C001 in marks 3 to 7 on the 528-cell 6C000 array, and the 6C011 for NTSC.[3][4][5]
The main sources are Ferranti's own files of 1981 to 1984, released as the Ferranti Archives 2026: specifications, logic and cell drawings, timing diagrams, test programs, memos, and correspondence with Sinclair Research and with Timex, which manufactured Spectrums and ZX81s for Sinclair at Dundee.[6] These are period factory documents. Many of them deal with production problems of 1983 and 1984. They help explain faults a repairer may meet, but they do not mean that every machine has those faults. The timing between the ULA and the RAM, and the refresh arrangements, are covered in more depth on Sinclair ZX Spectrum Memory Timing.
What the ULA does
[edit | edit source]Sinclair's service manual and Ferranti's drawings and test procedure describe these functions.[1][2][7]
| Function | How it works |
|---|---|
| Clocks | A 14 MHz crystal on pin 39 drives a counter chain. Half the crystal frequency, 7 MHz, is the pixel clock. A quarter, 3.5 MHz, leaves pin 32 as the CPU clock. |
| Video | The counters time a 64 µs line and a 312-line field. During the picture the ULA reads the bitmap and attribute bytes from the lower 16K of RAM itself, shifts the bitmap out a pixel at a time (bit 7 first), and picks the ink or paper colour from the attribute byte, which the November 1981 design sheet lays out as flash (bit 7), bright (bit 6), paper (bits 5 to 3) and ink (bits 2 to 0). The chip makes its own analogue outputs: inverted luminance with sync (Y, pin 17) and two colour-difference signals with colour burst (U and V, pins 15 and 16), each from a resistor-switched current stage driving an emitter follower.[8][9] On the board they feed the LM1889 encoder and the modulator. |
| Memory sharing | The ULA drives RAS, CAS, the write enable DRAMWE and the multiplexed address lines A0 to A6 of the lower 16K (IC6 to IC13). The CPU reaches the same RAM through the 74LS157 multiplexers IC3 and IC4 and series resistors R17 to R23, so that where both drive the address lines the ULA wins. If the CPU tries to use that RAM while the ULA needs it for the display, the ULA holds the CPU clock until its own access is complete.[1] Ferranti's test procedure checks that the clock is held during the active display when the CPU addresses memory with A14 high and A15 low, and during I/O cycles, and that it is released only at a fixed point in the ULA's own cycle.[7] |
| ROM select | ROMCS (pin 34) goes low when A14 and A15 are both low, that is when the CPU addresses the bottom 16K.[7] |
| Keyboard and tape input | An I/O read with A0 low (IORQ, RD and A0 low) puts the five keyboard column inputs KB0 to KB4 on data lines D0 to D4 and the EAR input on D6.[7][10] |
| Border, MIC and loudspeaker | An I/O write with A0 low (IORQ, WR and A0 low) latches the border colour from D0 to D2, MIC from D3 and the loudspeaker from D4. MIC, loudspeaker and EAR all use pin 28.[7] |
| Interrupt | Once per field the ULA pulls INT (pin 12) low for 9.14 µs.[11] Sinclair's manual says the CPU then runs the maskable interrupt routine, in which "the real-time is incremented and the keyboard is scanned".[1] |
Types and marks
[edit | edit source]A hand-drawn lineage chart, stapled in Ferranti's file to the telexes of September 1983, gives the family tree in two columns headed "UK PAL" and "USA NSTC" [sic]. The words on its arrows are Ferranti's; the chart does not explain them further.[5]
| Type | Column on the lineage chart | Earliest dates in the archive | What changed, as the documents record it | Board drawings and lists that name it |
|---|---|---|---|---|
| 5C102 | UK PAL | Specification issue 1, 14 December 1981; logic issue 4, 22 January 1982; Mk 3 logic issue 6, 10 March 1982[3][12][13] | The first type. Mk 3 adds gates after the LINE decode and at the shift-register input; the EAR input's feedback resistor changed from 3K4 on the Mk 1 to 4K4[14] | Issue 1 and Issue 2 (Sinclair parts list); "mod 1 (5C102 only)" on Sinclair's 1982 diagram[15][16][17] |
| 5C112 (-1, -2, -3) | UK PAL, also the head of the NTSC column | Logic issue 1, 30 June 1982[10] | Chart: "logic change". Title block: "an updated version of the ULA 5C102", same support drawings | Issue 2 ("Issue 2 mod" column); Timex Issue 3 drawing of June 1983: "5C112E or 5C112E-2 or 5C112E-3"[16][18] |
| 5C114 (Mk 2, Mk 3) | USA NTSC | Membrain package test, issue 3A, 3 December 1982[19] | Chart: "logic change" from the 5C112. No other document describes it | None in the archive |
| 6C001 Mk 3 | UK PAL | Specification and logic diagram issue 1, 26 August 1982[4][20] | Chart: "6C version" of the 5C112 | 6C001, mark not stated: Issue 3 in Sinclair's parts list; Issue 2 with changed resistors from May 1983[16][21] |
| 6C001 Mk 5 | UK PAL | Membrain part-probe test for the Mk 5, 15 April 1983[22] | Chart: "customer mods" (not described) | |
| 6C001 Mk 6 | UK PAL | Polaroids of 6C001-6 samples, 10 August 1983[23] | Chart: "new R64 osc" (not explained) | Photographed by Ferranti on Issue 2 and Issue 3 boards, August 1983[24] |
| 6C001 Mk 7 | UK PAL | Delays proposed 23 September 1983, agreed 29 September 1983; logic issue 3, 10 October 1983[5][25] | Chart: "customer mod delays": four inverters added in the CAS line and two in the address-select line | Timex Issue 6A drawing of September 1984: "6C-001E-7"; required from Issue 4A[26][27] |
| 6C011 Mk 2, Mk 3, Mk 4 | USA NTSC | Order of 22 May 1984 to bring the timing up to the 6C001 Mk 7; Mk 4 measured 31 July 1984[5][28] | Chart: Mk 2 from the 6C001 Mk 3 with "logic change + mods"; Mk 3 "new R64 osc"; Mk 4 "delays" |
Design history
[edit | edit source]November 1981: the first design sheets
[edit | edit source]The earliest Spectrum ULA documents in the archive are two hand-lettered sheets of November 1981: a logic design numbered "SRL81C-1" and dated 6 November 1981, and a timing sheet "ZX81C-2" dated 10 November 1981. Both use Ferranti's cell-library names; neither says who drew it.[2][29] Much of the finished design is already there:[2]
- a 14 MHz oscillator divided to 7 MHz and 3.5 MHz, a 64 µs line (15.625 kHz), a field of 312 lines at 50.08 Hz, and a final divide-by-32 stage for the flash rate (written as 1.565 Hz);
- an interrupt pulse of 9.14 µs;
- the attribute byte, written in blue ink as "F | B | PAPER | INK";
- the CPU clock stop when the CPU accesses the RAM during the display;
- address and RAS outputs that go to high impedance outside the display, noted "This allows refresh during non-active portion of frame";
- a ROMCS arrangement noted as "permitting use of 350 ns ROMs";
- a test mode that steps the counters when IORQ, MREQ, RD and WR are all asserted together.
The pin numbers on this sheet differ from the production pin-out (the oscillator is pin 1, for example). The timing sheet draws the display fetch as one RAS with two page-mode CAS cycles, the first for the bitmap byte and the second for the attribute byte, designed for "typically 75pF loading on RAS, CAS" and 35 pF on the address lines, with a budget of 21 ns for the skew of the CPU clock.[29]
December 1981 to March 1982: the 5C102
[edit | edit source]Ferranti's specification for the ULA 5C102, a "video display generator" on the "5C000 CML 440 cell array", is issue 1 of 14 December 1981 and issue 2 of 4 February 1982; the pinning drawing is dated 21 December 1981.[3] The logic diagram LD6701/ULA5C102/1 went through issues dated 14 December 1981 and 4, 12 and 22 January 1982, with support drawings for the flip-flop cells (26 January 1982), the analogue and output cells (8 February 1982) and the input and output cells (9 February 1982).[12][8][30] Four timing diagrams of 4 and 5 January 1982, two of them headed "5C102 Timing Diagram", set out the display fetch, the line and the field.[31][32][11]
The same drawing was reissued on 3 and 10 March 1982 as "ULA-5C102 MK3". Comparing the two prints, the Mk 3 adds three inverter-and-NOR stages after the LINE decode and a pair of NOR gates at the input of the first shift-register stage; the drawing does not say why.[13] Ferranti's test notes record one cell change between marks: the feedback resistor in the EAR input is 4.4K, and "was 3.4K on Mk 1".[14]
Sinclair's service manual says the 5C102 "has a timing fault which was cured by connecting a 74LS00 IC mounted on a miniature board and spider", and that this ULA was fitted to about 40,000 units.[15] Sinclair's own circuit diagram of 1982 carries the patch in pencil as "mod 1 (5C102 only)", and a torn sketch in Ferranti's file draws its wiring: gates of a 74LS00 between the Z80's A14 and A15 and the ULA's pins 36 and 37, combined with IORQ. As drawn, the gates make the ULA see A14 high and A15 low whenever IORQ is low.[17][33] The archive's file name for the sketch calls it the "dead cockroach" modification. The manual's list of Issue 1 board modifications also includes a 100 pF capacitor from RAS to ground, "necessary only when using ULA 5C102".[15]
June 1982: the 5C112
[edit | edit source]The 5C112 logic diagram, issue 1 of 30 June 1982, has a new job number (LD6761) and a title block reading "This is an updated version of the ULA 5C102. Support drawings are as per ULA-5C102". It keeps the 5C102 Mk 3 pin-out and both Mk 3 additions. The differences found by comparing the sheets are a chain of seven gates loaded with small capacitors (2.3 to about 8.4 pF) beside the K* latch, a modified output cell for CAS (drawn the next day with an added 2K5 pull-up and a 7 pF capacitor), and a 2K resistor to ground on the inside of the IORQ input. The drawings do not state the purpose of any of these.[10][8]
Sinclair's manual says the 5C112 "has no spider modification, but has either a diode or resistor or transistor connected to it": either a 4K7 resistor from +12 V to Z80 pin 30 with a 1N4148 from Z80 pin 30 to ULA pin 33, or a ZTX313 (TR6) with its base on Z80 pin 30 (A0), emitter on ULA pin 33 (IORQ) and collector on Z80 pin 11 (+5 V).[15] The same transistor connection is pencilled as "mod 2" on Sinclair's 1982 diagram, there drawn as a ZTX312.[17] For "all ULAs 5C112E-2 and later" the manual lists a change to the CPU clock buffer: D14 replaced by C67 (100 pF), R24 changed from 3K3 to 1K, R27 from 680R to 470R, and R73 (1K) added from IC1 pin 32 to +5 V.[15] The 1982 diagram has a pencilled "mod 3", dated 15 October 1982, with the same arrangement of a 1K series resistor with 100 pF across it into TR3 and a 1K pull-up.[17]
Ferranti's memos of early 1983 mention 5C112-1 parts with the date code 8234 and 5C112-2 parts with 8301, and a Polaroid in the file is labelled "5C112-3 (8320)".[34][35]
The 5C114
[edit | edit source]The 5C114 appears in only two places: a Membrain test program headed "5C114 MK2&3 PACKAGE TEST ISSUE 3A, 3-12-82", and the lineage chart, where it follows the 5C112 in the NTSC column after a "logic change".[19][5] Nothing else in the archive describes it.
August 1982 onwards: the 6C001
[edit | edit source]The 6C001 specification, issue 1 of 26 August 1982, puts the same functions and pin-out on the "6C000 CML 528 cell array", with lower typical supply currents.[4] Its logic diagram LD6790/ULA6C001/1 has issues of 26 August 1982, 14 February 1983 and 10 October 1983; the support drawings cover the flip-flop macros, the analogue cells (issues of 22 September 1982, 28 October 1982, 10 March 1983 and 15 June 1983) and the input and output cells (27 September 1982).[20][36][37][9][38]
Sinclair's manual says the 6C001 "alters the timing of the colour burst signal, and improves the performance of the Spectrum with certain television sets (e.g. Hitachi, Grundig). It also causes the screen picture to be shifted by one character width to the left."[15] In January 1983 Sinclair asked Ferranti to make the same colour-burst change on the NTSC ULA.[39]
Mark 5
[edit | edit source]The chart reaches the Mk 5 from the Mk 3 through "customer mods", which no document in the archive describes. A Membrain probe-test program for the "6C001 MK5" is dated 15 April 1983.[5][22] An undated set of Polaroids compares the RAS and CAS timing of 6C001-5 parts with a 5C112-3; one 6C001-5 is labelled "crashes cold", another "memory fail when warm".[35]
Mark 6
[edit | edit source]The chart's label for the Mk 6 is "new R64 osc". Between issue 3 (10 March 1983) and issue 4 (15 June 1983) of the analogue-cell drawing, the two collector resistors of the crystal oscillator changed from 1K5, circled in pencil "2k" on issue 3, to 2K1, and a 110R crossunder was added at the oscillator input.[37][9] No document says that this change is the "new R64 osc"; the dates fit, but the connection is an inference. On 10 August 1983 Ferranti photographed the RAS, A0 and CAS timing of 6C001-6 samples from material marked "Low R (3.8K)" on Issue 2 and Issue 3 boards; sample 4 "fails cold". The documents do not explain the "Low R" label.[23][24]
Mark 7
[edit | edit source]
On 23 September 1983 Ferranti asked Sinclair by telex to confirm two changes to the 6C001: four inverters added in the N.CAS line, increasing its delay by typically 22 ns at 25 °C, and two inverters in the ADSEL (address select) line, typically 11 ns, with worst-case delays up to 1.7 times those figures. Twenty-five engineering samples would follow four weeks after confirmation. Sinclair replied on 29 September 1983, copied to Timex: "The 6C001 mods as proposed 23.9.83 are agreed."[5] Issue 2 of the logic diagram (14 February 1983) has a box pencilled into the ADSEL line and labelled "EXTRA DELAY"; issue 3 (10 October 1983) has the added gates drawn in, and a print of it is marked in red "These 2 gates added on MK7 for ADSEL" and "These 4 gates added on MK7 for CAS".[40][25] The mark 7 is the 6C001E-7 that Timex's Issue 6A drawing calls for, and Sinclair's manual requires "ULA 6C001-7 or later" from the Issue 4A board onwards.[26][27] Why the delays were needed, and what they did to boards with different RAM, is covered on Sinclair ZX Spectrum Memory Timing.
The NTSC types: 5C114 and 6C011
[edit | edit source]In January 1983 Sinclair asked Ferranti for "another half dozen" NTSC Spectrum ULAs within a week or so.[39] On the lineage chart a struck-out branch from the 6C001 to a "6C011 Mk1" is replaced by a line from the 6C001 Mk 3 to the 6C011 Mk 2 ("logic change + mods"), followed by the Mk 3 ("new R64 osc") and the Mk 4 ("delays").[5] A Ferranti memo of 22 May 1984 records "an order to bring the NTSC Version timing up to the level of the ULA 6C001 MK7" and asks for 25 modified samples.[5] Ferranti's comparison of 31 July 1984 found the Mk 4's delays "not very different from MK3 devices" and "similar to the 6C001 MK7 version", with supply current up to 25 per cent higher than the Mk 3; five samples worked on the Timex test rig at a raised case temperature "with only a minor change in colours".[28]
1983: Timex's proposals for a larger ULA
[edit | edit source]On 24 May 1983 Timex sent Ferranti a RAS and CAS timing specification and proposed a 48-pin ULA: the Vcc2 dropper moved inside the package to free pin 13, a push-pull loudspeaker driver, and a pin for a Sinclair modification to the chroma-bias circuit. Timex wanted "full production quantities by late 1983".[41] Ferranti's notes of 2 June 1983 cost three options: a 40-pin revision (4416 RAM support with an extra address line, a clock output, no Vcc2) in about 12 weeks; a 48-pin version on a new 7K array adding RAS, CAS and write strobes for the 32K RAM and a piezo speaker output, at about £3.50 a unit and 16 weeks; or a 68-pin redesign that would also absorb the 74LS157 multiplexers, in 18 weeks.[42] Whether any of these was built is not recorded in the archive.
The 5C and 6C arrays compared
[edit | edit source]| Property | 5C102 and 5C112 (5C array) | 6C001 (6C array) |
|---|---|---|
| Base array | 5C000 CML, 440 cells[3] | 6C000 CML, 528 cells[4] |
| Typical supply current, Vcc1 (5 V) | 60 mA | 40 mA |
| Typical supply current, Vcc2 (2 V) | 120 mA | 80 mA |
| Input low current, general inputs | −0.6 mA max | −0.5 mA max |
| TAPE/LS high input current at 3 V | 6.0 mA max | 5.0 mA max |
| Input pull-up resistors | 16K[30] | 18K, a chain of 4K1, 4K1, 3K6, 3K1 and 3K1[38] |
| Totem-pole output pull-up | 200 Ω nominal[34] | 100 Ω nominal[34] |
| Gate delay, single current source, fan-in 1, fan-out 1, typical at 25 °C | 5.7 ns[43] | 4.8 ns[43] |
| Added delay per extra load (same table) | about 2.7 ns | about 2.5 ns |
| CPU clock output (pin 32) | Open collector with internal 2K pull-up[12] | Inverting resistive pull-up cell, 2K1[38] |
| INT output (pin 12) | Output with internal 5K pull-up (F43)[30] | Resistive pull-up cell (R40)[38] |
In February 1983 Ferranti noted that samples of 6C material "performed much better" for RAS signal integrity than the 5C112-2 parts it was investigating, and pointed to the lower totem-pole pull-up resistor.[34] The thresholds and output levels in the two specifications are otherwise the same.[3][4]
Pin-out and cell types
[edit | edit source]The 5C102, 5C112 and 6C001 share one pin-out.[3][10][20] Direction is as grouped in the specifications; the cell names are those on Ferranti's drawings (5C102 from the logic diagram, the cell sheet and the test notes; 6C001 from its cell sheet and logic diagram).[12][30][14][38][20]
| Pin | Signal | Direction | 5C102 cell | 6C001 cell | Notes |
|---|---|---|---|---|---|
| 1 | CAS (active low) | Output | F33 totem-pole; "F33 (modified)" on the 5C112 | R34 fast totem-pole | Column address strobe for the lower 16K |
| 2 | WR (active low) | Input | F1, 16K pull-up | EF1, 18K pull-up | |
| 3 | RD (active low) | Input | F1, 16K pull-up | EF1, 18K pull-up | |
| 4 | DRAMWE (active low) | Output | F33 totem-pole | R34 fast totem-pole | Write enable for the lower 16K |
| 5 | A0 | Input/output | F34 tristate, read back through an F1 input | R36 fast tristate, read back through EF4 | Multiplexed RAM address |
| 6 to 11 | A1 to A6 | Output | F34 tristate | R36 fast tristate | Multiplexed RAM address; high impedance when the CPU drives the RAM |
| 12 | INT (active low) | Output | F43, internal 5K pull-up | R40 resistive pull-up | One 9.14 µs low pulse per field |
| 13 | Vcc2 | Supply | 2 V nominal; fed from +5 V through R34 (15 Ω) on the board | ||
| 14 | Vcc1 | Supply | +5 V ±5% | ||
| 15 | U | Output | Analogue encoder stage with emitter-follower output | Colour difference, with burst | |
| 16 | V | Output | Analogue encoder stage with emitter-follower output | Colour difference, with burst | |
| 17 | Y (inverted) | Output | Analogue encoder stage with emitter-follower output | Luminance with sync; sync is the most positive level | |
| 18, 21, 22, 25, 27 | D0, D1, D2, D3, D4 | Input/output | F36 open collector, plus F1 input with 16K pull-up | R38 open collector, plus EF1 input with 18K pull-up | Keyboard bits out on a port read; border, MIC and speaker bits in on a write |
| 19 | KB0 | Input/output | Emitter-follower input, 16K pull-up, plus an open-collector output | EF3 three-Vbe emitter follower, 18K pull-up, plus an OC1 open-collector inverter pencilled "TEST OUTPUT" | Keyboard column |
| 20, 23, 24, 26 | KB1, KB2, KB3, KB4 | Input | Emitter-follower input, 16K pull-up | EF3 three-Vbe emitter follower, 18K pull-up | Keyboard columns |
| 28 | TAPE/LS | Input/output | Three-level output with an inverter input | Same function (TAPE/LS block with EAR, LS and MIC) | EAR in; MIC and loudspeaker out |
| 29 | D5 | Input only | F1, 16K pull-up | EF2, 18K pull-up with input crossunders and a 3K pull-down | Never driven by the ULA |
| 30 | D6 | Input/output | F36 open collector, plus F1 input | R38 open collector, plus EF1 input | EAR bit on a port read |
| 31 | D7 | Input only | F1, 16K pull-up | EF1, 18K pull-up | Never driven by the ULA |
| 32 | CPU clock (inverted) | Output | Open collector, internal 2K pull-up | RP1 inverting resistive pull-up (2K1) | 3.5 MHz; specified high level only 1.0 V at 1 mA |
| 33 | IORQ (active low) | Input | F1, 16K pull-up; the 5C112 adds a 2K resistor to ground inside | EF1, 18K pull-up | |
| 34 | ROMCS (active low) | Output | Inverting totem-pole (drawn as T.P on the logic diagram, listed as F33 in the test notes) | R34 fast totem-pole | |
| 35 | RAS (active low) | Output (tristate) | F34 tristate, driven through RTL2 | R36 fast tristate, driven through RTL2 | Row address strobe for the lower 16K |
| 36, 37 | A14, A15 | Input | F1, 16K pull-up | EF1, 18K pull-up | |
| 38 | MREQ (active low) | Input | F1, 16K pull-up | EF1, 18K pull-up | |
| 39 | OSC | Input | F64 crystal oscillator | XTAL OSC, buffered by RTL1 | 14 MHz crystal |
| 40 | GND | Supply | 0 V | ||
Both logic diagrams also show a pad for an internal signal BLACK*, marked "Bond pad for probe test only"; it is not bonded to a pin.[12][20] The ULA drives D0 to D4 and D6 only through open-collector outputs, so it can only pull those lines low; D5 and D7 are inputs only.[38][30]
Supplies
[edit | edit source]The ULA has two supply pins and one ground. Ferranti's specifications give Vcc1 as 5 V ±5% on pin 14 (operating range 4.75 to 5.25 V, 0 to 50 °C) and Vcc2 as "2 V (nominal)" on pin 13, with ground on pin 40.[3][4] Ferranti's package-test program for the 6C001 applies 2 V to pin 13; at probe test the 5C102 had an 18 Ω resistor connected between pins 13 and 14.[44][14]
On the board, pin 13 is fed from +5 V through R34, a 15 Ω resistor. Sinclair's Issue Two diagram shows R34 with C28, C29 and C30; Timex's Issue 3 drawing gives R34 15R, C29 47 nF and C30 47 nF, and its Issue 6A drawing R34 15R 0.5 W, C29 47 nF and C30 22 nF, with C28 22 µF on both.[45][18][26] On the Issue 3 drawing C30 is the capacitor at pin 13, with C28 and C29 on the +5 V side; the sketch in Timex's letter of May 1983 has C29 and C30 the other way round.[18][41] Sinclair's service manual tells the engineer to check pin 13 for about +3 V, and for distorted video to check it and change C30.[46] Ferranti's specifications say 2 V nominal; the documents do not reconcile the two figures. The voltage at pin 13 is the +5 V rail less the drop across R34, so it falls as the ULA draws more current.
That drop is how Ferranti measured supply current. Its comparison of NTSC 6C011 ULAs in July 1984 records "the volt drop across the 15Ω dropper resistor for Vcc": 1.20 V on a Mk 3 and 1.44 to 1.48 V on three Mk 4 parts.[28] At 15 Ω those are about 80 mA and 96 to 99 mA. The same reading taken across R34 on a working board gives the current into pin 13.
| Type | Vcc1 (pin 14) | Vcc2 (pin 13) | Conditions and source |
|---|---|---|---|
| 5C102 | 60 mA typical | 120 mA typical | Specification, 4 February 1982[3] |
| 6C001 | 40 mA typical | 80 mA typical | Specification, 26 August 1982[4] |
| 5C112 returns | 48 to 68.5 mA | 101 to 143 mA | Measured with Vcc1 5.00 V and Vcc2 2.4 V, February 1983[47] |
| 6C011 Mk 3 | 1.20 V across the 15 Ω dropper, about 80 mA | July 1984[28] | |
| 6C011 Mk 4 | 1.44 to 1.48 V across the 15 Ω dropper, about 96 to 99 mA; "up to 25% larger" than the Mk 3 | July 1984[28] | |
The +5 V rail matters as well. In November 1984 Ferranti told Timex that its sampling had found Vcc-sensitive devices, working at 5 V and above but failing at some point below, and that it might need to specify a minimum Vcc; Timex undertook to check its boards for voltage drop along the tracks.[48] One of the keyboard rejects examined that month worked "cold at just over 5.0v dropping to 4.81V when warmed up".[49] Sinclair's manual already tells the engineer to check IC1 pin 14 for +5 V "with no discernible ripple".[46] On a machine with marginal ULA behaviour, measure the +5 V at the ULA itself as well as at the regulator.
Input thresholds, tape pin and video levels
[edit | edit source]These figures are Ferranti's specification limits, design calculations and bench-test values for the bare chip. They are not service figures for a working board, where the surrounding components load every pin.
| Inputs | Low level, maximum | High level, minimum |
|---|---|---|
| All inputs except the keyboard and TAPE/LS | 0.8 V | 2.0 V |
| KB0 to KB4 (pins 19, 20, 23, 24, 26) | 1.4 V | 2.8 V |
| TAPE/LS (pin 28, EAR input) | 0.4 V | 1.0 V |
The outputs are specified at 0.5 V low (sinking 16 mA on RAS, CAS, DRAMWE, ROMCS and A0 to A6; 8 mA on INT, D0 to D4 and D6) and at least 2.4 V high. The CPU clock output is specified at 0.3 V low and only 1.0 V high, each at 1 mA.[3][4] On the board the clock goes through the transistor TR3, which Sinclair's manual says "ensures that the clock amplitude is +5V rather than some arbitrary TTL level".[1] Ferranti's data for the 6C array family in general gives a totem-pole output high level of 2.4 to 3.1 V, so a ULA output that rises only to about 3 V is not in itself a fault.[43]
TAPE/LS (pin 28)
[edit | edit source]The pin is a three-level output for the loudspeaker and MIC and an input for EAR. Ferranti's handwritten test procedure for the 5C102 gives these limits, with the port bits written by the CPU (D4 loudspeaker, D3 MIC); the design calculation in the test notes gives the middle values, and the 5C102 cell drawing has "745 mV" written at the pin.[7][14][8]
| D4 (loudspeaker) | D3 (MIC) | Test limit | Design value |
|---|---|---|---|
| 1 | 1 | Above 3.7 V | 4.0 V |
| 0 | 1 | 0.65 to 0.85 V | 0.74 V |
| 0 | 0 | Below 0.3 V | 0.24 V |
With the MIC and speaker bits set for the middle level, the procedure expects D6 to read 1 with 1 V on the pin and 0 with 0.5 V, noting that these "may be reversed depending on layout of peripheral cells".[7]
Video outputs
[edit | edit source]Ferranti's design model of the 5C102's Y output, into a 1K load, gives 2.40 V for black, 2.10 V red, 1.79 V green, 2.25 V blue, 1.00 V for bright white and about 4.1 V for sync, the most positive level because the output is inverted.[14] The test procedure gives U and V as a black level plus a change for each colour bit, the bits adding together:[7]
| Output | Black | Blue bit | Red bit | Green bit | Burst |
|---|---|---|---|---|---|
| U | 2.011 V | −0.963 V | +0.321 V | +0.642 V | 0.876 V |
| V (even lines) | 1.928 V | −0.227 V | +1.364 V | −1.136 V | +0.909 V |
On odd lines the V changes reverse sign. The procedure works magenta on U as 2.011 − 0.963 + 0.321 = 1.369 V, notes that white comes out the same as black on U, and suggests a tolerance of about ±20 mV. Ferranti's design models in the test notes give different reference levels (U 2.96 V, V 3.27 V); the documents do not say why the two sets differ.[7][14]
Video and frame timing
[edit | edit source]| Item | Value | Source |
|---|---|---|
| Master clock | 14 MHz crystal on pin 39 | [2][45] |
| Pixel clock | 7 MHz | [2] |
| CPU clock | 3.5 MHz, a quarter of the master clock, on pin 32 | [2][7] |
| Line | 64 µs: 896 oscillator cycles, 448 pixel clocks | [50][2] |
| Active part of a line | 4/7 of the line (256 of the 448 pixel clocks) | [7][32] |
| Line structure | Active display, then blanking containing line sync and colour burst | [32] |
| Field | 312 lines: 279,552 oscillator cycles, about 50.08 Hz | [50][2] |
| Display lines | 192 per field | [11][7] |
| Field sync | Four lines, covered by blanking | [11] |
| Interrupt | One low pulse of 9.14 µs per field on pin 12, starting with the field sync | [11][2] |
| Flash | A counter stage with a period of 32 fields, 16 fields each way; the 1981 sheet writes 1.565 Hz | [50][2] |
| Display fetch | In each 16-pixel window, two RAS cycles, each with two page-mode CAS cycles: bitmap byte, then attribute byte | [31][29] |
During each fetch the ULA latches the bitmap byte (DLATCH) and the attribute byte (ALATCH) and loads an eight-bit shift register (SLOAD) for the next eight pixels.[31][2] A missing interrupt, or one of the wrong width, points at the ULA or its clock; INT is easy to check with an oscilloscope on pin 12. The RAM timing limits behind the fetch are on Sinclair ZX Spectrum Memory Timing.
The Spectrum+ keyboard faults of November 1984
[edit | edit source]On 7 November 1984 Timex wrote to Ferranti about "a high fallout rate of Ferranti ULA-7" with keyboard faults since the introduction of the ZX+ keyboard. Timex saw two kinds: chips that showed columns of "invisible keys" permanently, whatever the keyboard, and chips that showed the wrong keys in a column pair, so that pressing 7 could display V, J, N, 4, R, F or C at random. Timex's oscilloscope photographs showed the new keyboard slowing the rise time on a keyboard line from 330 ns to about 1500 ns and increasing crosstalk between columns. The ULAs also failed Timex's new Zehntel automatic tester, which drives patterns into the keyboard pins with no keyboard connected.[51]
Ferranti's memo of 11 November 1984 examined five returned 6C001-7 parts. All had passed Ferranti's TV test, slot test and Membrain test again, except that one was suspect on Membrain with high supply current. The new six-layer membrane gave about 100 pF on each ULA keyboard input, about three times the old two-layer keyboard, but a good ULA still worked with more than 220 pF added. Ferranti then measured the switching threshold of each keyboard input:[49]
| Device | Issue 3 board, old keyboard | Issue 6A board, Spectrum+ keyboard | Finding |
|---|---|---|---|
| 2 | Fail: columns 3 and 4 dead | Fail: columns 3 and 4 dead | Internal short between pins 23 and 24 (KB2 and KB3); worked only with Vcc below 3.67 V or with both pins driven low together |
| 3 | Fail: column 4 dead | Fail: column 4 dead | Threshold of about 0.7 V on pin 24 (KB3); also Vcc-sensitive |
| 4 | Fail cold: column 5 dead | Fail: some keys in column 5 marginal | Threshold 3.71 V on pin 26 (KB4) |
| 5 | Pass | Fail: some keys in column 5 marginal, OK hot | Threshold 4.03 V on pin 26 (KB4) |
| 6 | Pass | Fail: some keys in the column the memo numbers 7 marginal | Threshold 3.72 V on pin 24 (KB3) |
The other keyboard inputs on these chips switched at about 2.0 to 2.1 V. Thresholds above the specified 2.8 V minimum, with the slower edges of the new membrane, would give "an excessively long pulse at the ULA input", which Ferranti thought upset the keyboard read routine. The parts had passed the Membrain test because it drove every input from an open-collector TTL driver with a 10K pull-up, so the chip saw 0.2 V and 5.0 V, and because it drove all five keyboard inputs together.[49] By 21 November 1984 the Membrain program had been changed to catch the pin-to-pin short and a small addition to the buffer board let the tester reject the threshold faults; "We can now reject all 5 returns on our Membrain". The change was to go in at final package test.[52] That memo gives the high-threshold pins as "pins 25 or 27"; on the pin-out those are data lines, and the threshold table in the earlier memo shows pins 24 and 26.[52][49] A slot-test printout of the same parts survives, but its test numbers are not mapped to parameters anywhere.[53]
For a repairer: a whole column of keys dead, or wrong characters from one column, can come from the ULA as well as from the membrane, and the fault followed the ULA from board to board in Ferranti's tests. The ULA is socketed on every board, so substituting a known-good one is a quick test. See also Sinclair ZX Spectrum Keyboard Membrane Repair and Sinclair ZX Spectrum+ Troubleshooting Guide.
Field failures, warranty and second sources
[edit | edit source]In February 1983 Sinclair, Timex and Ferranti met over ULA rejects in Spectrum and ZX81 production at Timex; the agenda notes 48 Spectrum 5C112 rejects at Dundee.[6] Ferranti's investigation of those parts, and the refresh resistor R57 at the centre of it, are described on Sinclair ZX Spectrum Memory Timing.
Ferranti's report of a meeting at Timex on 14 November 1984 records:[48]
- Ferranti said it had been achieving better than 0.1 per cent failures; Timex said it was still seeing up to 1.4 per cent.
- Ferranti's own sampling had found Vcc-sensitive devices. Each batch was now sampled at 0.65 per cent AQL after the TV and Membrain tests, and 5 of 35 batches had failed.
- Timex complained about Ferranti's 12-month warranty, particularly as it was still receiving ULAs with 1983 date codes. Ferranti agreed to extend it to 18 months on "the Spectrum 6C only", to be confirmed in writing. Timex said other major vendors, "including AMI", gave two years.
- Timex said it might have up to 30,000 pieces of "the AMI ULA" going through its lines, but would not say more or give a sample. The Ferranti author suspected pressure, since two weeks earlier Timex had said it had received 200 pieces and that was all it had on order.
- Timex raised the increased capacitance of the Spectrum+ membrane and took two of the new keyboards to Ferranti for investigation.
Sinclair's service manual says the Issue 6A board "can be fitted with either a Ferranti or a Saga main ULA".[27] The Ferranti files say nothing about that part.
How Ferranti tested the ULA
[edit | edit source]In November 1984 Ferranti retested returned 6C001s on its TV test, slot test and Membrain test.[49] The table lists what the archive holds on Ferranti's testing.
| Stage | What the documents show |
|---|---|
| Membrain programs | Membrain was the IC tester. Three program listings survive: a package test for the "5C114 MK2&3" (3 December 1982, current limit 400 mA), a part-probe test for the "6C001 MK5" (15 April 1983, 300 mA) and a package test for the 6C001 (27 June 1983). Each connects ground to pin 40 and +5 V to pin 14, and takes pins 13, 15 to 17 and 39 (and on the package tests pin 28) off the tester's drivers. The sections run in the order of Ferranti's handwritten 5C102 procedure: counter, keyboard, interrupt, CPU read and write, CPU halting, row and column address reads, sync, dot pattern and shift register, bright, border, tape and loudspeaker, EAR, U and V, blanking and flash. The package test adds level measurements on Y and U for each colour.[19][22][44][7] |
| Analogue jigs | The 5C102 test notes design the extra circuits: an 18 Ω resistor between pins 13 and 14 at probe, a buffer for the crystal pin, a tristate tester that tries to pull A0 to A6 and RAS low, window comparators on Y, U and V with 1K loads, and for the package test a sample-and-hold feeding a Ferranti ZN429 8-bit D/A converter.[14] |
| TV test boxes | These were built from Spectrum boards. A Ferranti applications memo of early 1983 noted that some had R57 fitted and some did not, and asked for a directive on which way to build them.[34] |
| Functional test box | From June to October 1983 Ferranti built a test box round an Issue 3 Spectrum board with a zero-insertion-force socket in the ULA position, driven by a second "master" Spectrum. Its test program shows colour bars, steps the border through all eight colours, plays beeps and saves to tape, with the operator judging the result. See Ferranti Spectrum ULA Test Box.[54][55] |
| Return testing | Returned parts were soak-tested in a real board. In February 1983 each of 43 returned 5C112-2s was run in an Issue 2 board with R57 removed, playing games including "Invaders", "Horace" and "Kong" for 5 to 25 minutes each.[47] |
Identifying a ULA and the board it belongs on
[edit | edit source]Ferranti's type numbers carry a letter suffix and a mark number after the hyphen. Timex's drawings call for "5C112E or 5C112E-2 or 5C112E-3" (Issue 3) and "6C-001E-7" (Issue 6A), and Sinclair's manual says that "the issue number is designated by the number after the hyphen".[18][26][27] Ferranti's memos quote four-digit date codes such as 8234 and 8301.[34]
| Board | ULA named | Source |
|---|---|---|
| Issue 1 | 5C102: the manual's Issue 1 modification list refers to it, and it was fitted to about 40,000 units against about 26,000 Issue 1 boards, with the 74LS00 "spider" modification | Sinclair service manual, sections 4.1.2 and 4.2[15] |
| Sinclair diagram annotated to 15 October 1982 | "mod 1 (5C102 only)", mods 2 and 3 for later parts | SPEC-SIN-SCH-068[17] |
| Issue 2 | 5C102; 5C112 in the "Issue 2 mod" column; 6C001 permitted from May 1983 with four resistors changed | Sinclair parts list; Sinclair telex of 26 May 1983[16][21] |
| Issue 3 | Timex's drawing of June 1983: "5C112E or 5C112E-2 or 5C112E-3 (see mod. shts)". Sinclair's parts list: 6C001. Ferranti tested 6C001-6 parts on Issue 3 boards in August 1983 | SPEC-TMX-SCH-074; Sinclair parts list; SPEC-FER-REP-050[18][16][23] |
| Issues 4A and 4B | "ULA 6C001-7 or later" required: two spare gates of IC24 are in series with the RAS output | Sinclair supplement, section 9.5[27] |
| Issue 6A | Timex's drawing of September 1984 ("Ferranti version"): 6C-001E-7. Sinclair: Ferranti or Saga | SPEC-TMX-SCH-069; Sinclair supplement, section 9.9[26][27] |
The Issue 3 entries disagree: Timex's Issue 3 drawing of June 1983 names only 5C112 parts, while Sinclair's parts list gives the 6C001 for Issue 3. Sinclair's telex of May 1983 also gives resistor values for a 6C001 on an Issue 3 board, so both families were in use on that issue.[18][16][21]
Fitting a 6C001 to an Issue 2 board needs four resistor changes. The values, from Sinclair's manual and its telex of 26 May 1983, are on Sinclair ZX Spectrum General Maintenance.
When swapping ULAs, bear in mind that the marks differ inside: the Mk 7 has typically 22 ns more delay on CAS and 11 ns more on address select than the Mk 6, and in Ferranti's 1984 tests a board that worked with one Mk 7 failed with other Mk 7 parts about 10 ns faster.[5][56] A ULA that fails in one board can work in another, and the reverse. Sinclair ZX Spectrum Memory Timing covers this in detail.
Related pages
[edit | edit source]- Sinclair ZX Spectrum
- Sinclair ZX Spectrum Memory Timing
- Sinclair ZX Spectrum General Maintenance
- Sinclair ZX Spectrum Troubleshooting Guide
- Sinclair ZX Spectrum Service Manual
- Sinclair ZX Spectrum Keyboard Membrane Repair
- Sinclair ZX Spectrum 128 ULA
- Sinclair ZX81 ULA
- Ferranti Spectrum ULA Test Box
- Ferranti Archives 2026: the collection of Ferranti files, with every scan in Category:Ferranti Archives 2026
References
[edit | edit source]- ↑ 1.0 1.1 1.2 1.3 1.4 ZX Spectrum Service Manual, Sinclair Research Ltd, sections 1.3 (CPU control signals, CPU clock and TR3, dynamic memory refresh) and 1.5.2 (standard 16k RAM) (pp. 8–10). Hosted as Sinclair ZX Spectrum Service Manual (PDF). Source for the interrupt routine, the clock buffer, contention and the address multiplexing.
- ↑ 2.00 2.01 2.02 2.03 2.04 2.05 2.06 2.07 2.08 2.09 2.10 2.11 Hand-lettered logic design "SRL81C-1", 6 November 1981, Ferranti Archives 2026 (SPEC-UNK-SCH-070). Source for the counter chain and its frequencies, the 9.14 µs interrupt, the attribute byte, contention, the high-impedance RAS and address outputs, the ROMCS note and the test mode. The sheet uses Ferranti's cell names but does not say who drew it.
- ↑ 3.00 3.01 3.02 3.03 3.04 3.05 3.06 3.07 3.08 3.09 Ferranti ULA 5C102 specification, "Video display generator", issue 2, 4 February 1982, with the pinning drawing of 21 December 1981, Ferranti Archives 2026 (SPEC-FER-DAT-093). Source for the 5C000 440-cell array, package, temperature and supply ranges, typical supply currents, input thresholds, output levels and the pin-out.
- ↑ 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Ferranti ULA 6C001 specification, issue 1, 26 August 1982, Ferranti Archives 2026 (SPEC-FER-DAT-097). Source for the 6C000 528-cell array and the 6C001's supply currents, thresholds and output levels.
- ↑ 5.00 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 5.09 Ferranti lineage chart of Spectrum ULA types, Ferranti telex of 23 September 1983, Sinclair telex of 29 September 1983 and Ferranti memo of 22 May 1984, Ferranti Archives 2026 (SPEC-FER-FAX-MEM-048). Source for the PAL and NTSC lineage, the mark 7 delays and the 6C011 order.
- ↑ 6.0 6.1 Agenda for the Sinclair, Timex and Ferranti meeting of 11 February 1983, Ferranti Archives 2026 (SPEC-UNK-AGN-061). Source for ULA rejects in Spectrum and ZX81 manufacture at Timex, Dundee, and the 48 Spectrum 5C112 rejects.
- ↑ 7.00 7.01 7.02 7.03 7.04 7.05 7.06 7.07 7.08 7.09 7.10 7.11 7.12 Ferranti handwritten test procedure "ULA5C102 Testprogram", undated, Ferranti Archives 2026 (SPEC-FER-NOT-094). Source for the keyboard, border, MIC and speaker port bits, the contention and ROMCS tests, the 4/7 active line, the TAPE/LS and EAR limits and the U and V test values.
- ↑ 8.0 8.1 8.2 8.3 Ferranti drawing ULA5C102/3, analogue and output cells, issue 3, 1 July 1982, Ferranti Archives 2026 (SPEC-FER-SCH-109). Source for the 5C102 video encoder stages, the TAPE/LS cell with "745 mV" at the pin, and the "F33 (MODIFIED)" CAS cell.
- ↑ 9.0 9.1 9.2 Ferranti drawing ULA 6C001/3, issue 4, 15 June 1983, Ferranti Archives 2026 (SPEC-FER-SCH-016). Source for the on-chip Y, U and V stages, the 2K1 oscillator resistors and the 110R crossunder added at issue 4.
- ↑ 10.0 10.1 10.2 10.3 Ferranti logic diagram LD6761/ULA5C112/1, issue 1, 30 June 1982, Ferranti Archives 2026 (SPEC-FER-SCH-112). Source for the 5C112 as "an updated version of the ULA 5C102", its capacitor-loaded gate chain, modified CAS cell, the 2K resistor on IORQ, and the pencilled IORQ, RD and A0 inputs of the keyboard strobe.
- ↑ 11.0 11.1 11.2 11.3 11.4 "5C102 Timing Diagram 4", field timing and interrupt, 5 January 1982, Ferranti Archives 2026 (SPEC-FER-NOT-080). Source for 312 lines per field, 192 display lines, the four-line field sync and the 9.14 µs INT pulse.
- ↑ 12.0 12.1 12.2 12.3 12.4 Ferranti logic diagram LD6701/ULA5C102/1, issue 4, 22 January 1982, Ferranti Archives 2026 (SPEC-FER-SCH-113). Source for the 5C102 issue dates and the cell used at each pad, including the open-collector CPU clock with 2K pull-up and the BLACK* probe pad.
- ↑ 13.0 13.1 The same drawing retitled "ULA-5C102 MK3", issue 6, 10 March 1982, Ferranti Archives 2026 (SPEC-FER-SCH-114). Source for the Mk 3 issue dates and the gates added after LINE and at the shift-register input.
- ↑ 14.0 14.1 14.2 14.3 14.4 14.5 14.6 14.7 Ferranti ULA 5C102 specification (photocopy) with handwritten probe-test and package-test notes, Ferranti Archives 2026 (SPEC-FER-DAT-089). Source for the 5C102 cell at each pin, the Y, U, V and TAPE/LS design models, the EAR feedback resistor "was 3.4K on Mk 1", and the probe and package test jigs including the 18 Ω between pins 13 and 14.
- ↑ 15.0 15.1 15.2 15.3 15.4 15.5 15.6 ZX Spectrum Service Manual, Sinclair Research Ltd, section 4.1.2 "Modification History" and section 4.2 "Modifications – Issue 1 Board" (pp. 21–22). Hosted as Sinclair ZX Spectrum Service Manual (PDF). Source for the 5C102 spider modification, the 5C112 diode, resistor and transistor modifications, the CPU clock changes for 5C112E-2 and later, the 100 pF RAS capacitor for the 5C102 and Sinclair's description of the 6C001.
- ↑ 16.0 16.1 16.2 16.3 16.4 16.5 ZX Spectrum Service Manual, Sinclair Research Ltd, sections 8.2, 8.10 and 8.11 (pp. 41–45): notes to the parts list and the IC and resistor lists for Issue 2, Issue 2 Mod and Issue 3. Hosted as Sinclair ZX Spectrum Service Manual (PDF).
- ↑ 17.0 17.1 17.2 17.3 17.4 Sinclair Research ZX Spectrum circuit diagram, 1982, with pencilled modifications mod 1 to mod 3 (mod 3 dated 15 October 1982), Ferranti Archives 2026 (SPEC-SIN-SCH-068). Source for "mod 1 (5C102 only)", the transistor of mod 2 and the clock buffer of mod 3.
- ↑ 18.0 18.1 18.2 18.3 18.4 18.5 Timex Corporation (Dundee) "ZX Spectrum Circuit Diag. Issue 3", drawing 356-201891-02, 10 June 1983, Ferranti Archives 2026 (SPEC-TMX-SCH-074). Source for the 5C112E ULA call-out and for R34, C28, C29 and C30 and their positions (read from the drawing).
- ↑ 19.0 19.1 19.2 Ferranti Membrain program "5C114 MK2&3 package test", issue 3A, 3 December 1982, Ferranti Archives 2026 (SPEC-FER-COD-090). Source for the 5C114 and its tester set-up.
- ↑ 20.0 20.1 20.2 20.3 20.4 Ferranti logic diagram LD6790/ULA6C001/1, issue 3, 10 October 1983 (issues 1 and 2: 26 August 1982 and 14 February 1983), Ferranti Archives 2026 (SPEC-FER-SCH-017). Source for the 6C001 pad list, the KB0 "test output" and the BLACK* probe pad.
- ↑ 21.0 21.1 21.2 Sinclair telex to Ferranti amending Engineering Instruction/Spectrum 309, 26 May 1983, Ferranti Archives 2026 (SPEC-SIN-FAX-056). Source for the use of the 6C001 on Issue 2 boards and the resistor values for Issue 2 and Issue 3 boards.
- ↑ 22.0 22.1 22.2 Ferranti Membrain program "6C001 MK5 part probe test", issue 2, 15 April 1983, Ferranti Archives 2026 (SPEC-FER-COD-091). Source for the Mk 5 date and the test sequence.
- ↑ 23.0 23.1 23.2 Ferranti record of RAS, A0 and CAS Polaroids of 6C001-6 ULAs on Issue 2 and Issue 3 boards, cold, hot and with 150 pF on CAS, 10 August 1983, Ferranti Archives 2026 (SPEC-FER-REP-050). Source for the "Low R (3.8K)" samples and sample 4 "fails cold".
- ↑ 24.0 24.1 Ferranti envelope and Polaroids of 6C001-6 "Low R" ULAs on Issue 2 and Issue 3 boards, 10 August 1983, Ferranti Archives 2026 (SPEC-FER-POL-066).
- ↑ 25.0 25.1 25.2 The same drawing, black-line print with red-pen notes "These 2 gates added on MK7 for ADSEL" and "These 4 gates added on MK7 for CAS", Ferranti Archives 2026 (SPEC-FER-SCH-018). Source for the gates added on the mark 7.
- ↑ 26.0 26.1 26.2 26.3 26.4 Timex Corporation (Dundee) "ZX Spectrum Circuit Diag. Issue 6A", Ferranti version, drawing 356-280106-01, 25 September 1984, Ferranti Archives 2026 (SPEC-TMX-SCH-069). Source for the 6C-001E-7 call-out and R34 15R 0.5 W, C29 47 nF and C30 22 nF.
- ↑ 27.0 27.1 27.2 27.3 27.4 27.5 ZX Spectrum Service Manual, Sinclair Research Ltd, Supplement No. 1, sections 9.5 (Issue 4A), 9.9 (Issue 6A) and 9.19 (integrated circuits) (pp. 50–55). Hosted as Sinclair ZX Spectrum Service Manual (PDF). Source for the 6C001-7 requirement from Issue 4A, the mark numbering and the Ferranti or Saga ULA on Issue 6A.
- ↑ 28.0 28.1 28.2 28.3 28.4 Ferranti handwritten comparison of 6C011 Mk 4 and Mk 3 ULAs with oscilloscope photographs, 31 July 1984, Ferranti Archives 2026 (SPEC-FER-MEM-047). Source for the dropper voltages and the Mk 4's delays, supply current and high-temperature test.
- ↑ 29.0 29.1 29.2 Timing sheet "ZX81C-2", video cycle, CPU memory cycle and CPU clock skew, 10 November 1981, Ferranti Archives 2026 (SPEC-FER-SCH-073). Source for the page-mode display fetch, the loading figures and the 21 ns clock skew budget.
- ↑ 30.0 30.1 30.2 30.3 30.4 Ferranti drawing ULA 5C102/4, input and output cells, issue 1, 9 February 1982, Ferranti Archives 2026 (SPEC-FER-SCH-111). Source for the 5C102 I/O cells, their 16K pull-ups and the F43 INT output.
- ↑ 31.0 31.1 31.2 5C102 timing diagram sheet 1, display memory fetch, with a faint pencil date read as 4 January 1982, Ferranti Archives 2026 (SPEC-FER-NOT-077). Source for two RAS cycles of two CAS each in every 16-cycle fetch window, and for the DLATCH, ALATCH and SLOAD timing.
- ↑ 32.0 32.1 32.2 "5C102 Timing Diagram 3", line timing, 4 January 1982, Ferranti Archives 2026 (SPEC-FER-NOT-079). Source for the line structure of active display, blanking, sync and burst.
- ↑ Pen sketch of a 74LS00 patch gating A14 and A15 with IORQ, undated, Ferranti Archives 2026 (SPEC-FER-SCH-075). Source for the gate wiring of the 5C102 patch.
- ↑ 34.0 34.1 34.2 34.3 34.4 34.5 Ferranti memo "Timex 5C112-2 returns (date coded 8301)", about February 1983, with Polaroids, Ferranti Archives 2026 (SPEC-FER-MEM-058). Source for the 5C and 6C totem-pole pull-ups, the date codes, and the TV test boxes with and without R57.
- ↑ 35.0 35.1 Ferranti envelope and Polaroids comparing RAS and CAS timing of 6C001-5 and 5C112-3 ULAs, undated, Ferranti Archives 2026 (SPEC-FER-POL-065). Source for the "crashes cold" and "memory fail when warm" labels and the "5C112-3 (8320)" print.
- ↑ Ferranti drawing LD6790/ULA6C001/2, flip-flop macros, issue 3, 2 March 1983, Ferranti Archives 2026 (SPEC-FER-SCH-014). Source for the 6C001 support drawing set.
- ↑ 37.0 37.1 Ferranti drawing ULA 6C001/3, video encoder, crystal oscillator and tape interface, issue 3, 10 March 1983, Ferranti Archives 2026 (SPEC-FER-SCH-076). Source for the 1K5 oscillator collector resistors circled "2k".
- ↑ 38.0 38.1 38.2 38.3 38.4 38.5 Ferranti drawing ULA 6C001/4, input and output cell circuits, issue 1, 27 September 1982, Ferranti Archives 2026 (SPEC-FER-SCH-015). Source for the 6C001 cell type at each pin and the 18K pull-up chain.
- ↑ 39.0 39.1 Sinclair Research letter to Ferranti, 28 January 1983, Ferranti Archives 2026 (SPEC-SIN-LET-043). Source for the request for more NTSC Spectrum ULAs and for the 6C001 colour-burst change to be made on the NTSC ULA.
- ↑ Ferranti logic diagram LD6790/ULA6C001/1, issue 2, 14 February 1983, Ferranti Archives 2026 (SPEC-FER-FOL-020). Source for the pencilled "extra delay" box in the ADSEL line before the mark 7 gates were drawn in.
- ↑ 41.0 41.1 Timex Corporation (Dundee) letter to Ferranti, "ZX Spectrum ULA modification", 24 May 1983, with figures C to E, Ferranti Archives 2026 (SPEC-TMX-LET-049). Source for the sketch of the Vcc2 dropper (R34, 15 Ω) and the 48-pin proposals.
- ↑ Ferranti notes "Timex - mods", 2 June 1983, Ferranti Archives 2026 (SPEC-FER-NOT-054). Source for the 40, 48 and 68-pin options.
- ↑ 43.0 43.1 43.2 Ferranti ULA array data pages, gate-delay tables hand-labelled "5C" and "6C", and 6C array electrical characteristics, undated, Ferranti Archives 2026 (GEN-FER-SCH-063). Source for the typical gate delays and the 2.4 to 3.1 V output high level.
- ↑ 44.0 44.1 Ferranti Membrain program "ULA 6C001 SAM test program (packages only)", issue 2, 27 June 1983, Ferranti Archives 2026 (SPEC-FER-COD-092). Source for Vcc1 on pin 14, Vcc2 2 V on pin 13, ground on pin 40, and the Y and U level tests.
- ↑ 45.0 45.1 Sinclair Research "ZX Spectrum Circuit Diagram – Issue Two", SRC 102, 16 August 1982, Ferranti Archives 2026 (SPEC-SIN-SCH-071). Source for the 14 MHz crystal and R34 with C28 to C30 on pin 13.
- ↑ 46.0 46.1 ZX Spectrum Service Manual, Sinclair Research Ltd, sections 5.3.1, 6.3 and 6.4 (pp. 26–33): the checks of IC1 pin 14 for +5 V with no discernible ripple and of pin 13 for +3 V. Hosted as Sinclair ZX Spectrum Service Manual (PDF).
- ↑ 47.0 47.1 Ferranti test notes on 5C112-2 ULAs returned by Timex, 22 February 1983, Ferranti Archives 2026 (SPEC-FER-NOT-057). Source for the measured supply currents and the soak tests.
- ↑ 48.0 48.1 Ferranti report on a visit to Timex, 14 November 1984, Ferranti Archives 2026 (SPEC-FER-REP-038). Source for the failure rates, the Vcc-sensitive devices, the AQL sampling, the warranty extension and the AMI ULA.
- ↑ 49.0 49.1 49.2 49.3 49.4 49.5 Ferranti memo "Spectrum+ 6C001-7 keyboard failures", 11 November 1984, Ferranti Archives 2026 (SPEC-FER-MEM-039). Source for the board tests, the membrane capacitance, the threshold table, the Vcc-sensitive device and the Membrain drive levels.
- ↑ 50.0 50.1 50.2 Counter-chain timing diagrams, undated, Ferranti Archives 2026 (SPEC-FER-NOT-081). Source for 896 oscillator cycles per line, 279,552 per field and the 32-field flash stage.
- ↑ Timex Corporation (Dundee) letter to Ferranti, "Spectrum ULA-7 Failure Analysis, Keyboard Faults", 7 November 1984, with oscilloscope Polaroids, Ferranti Archives 2026 (SPEC-TMX-LET-041). Source for the two fault categories, the rise times, crosstalk and the Zehntel tests.
- ↑ 52.0 52.1 Ferranti memo "ULA6C001 returns", 21 November 1984, Ferranti Archives 2026 (SPEC-FER-MEM-040). Source for the three fault types and the Membrain program and buffer board changes.
- ↑ Ferranti slot test printout for 6C001 keyboard rejects, 15 November 1984, Ferranti Archives 2026 (SPEC-FER-REP-042). The test numbers are not explained in the document.
- ↑ Ferranti layout sketch of the Spectrum Test Box Mk 1, 21 June 1983, Ferranti Archives 2026 (SPEC-FER-SCH-144). Source for the test box built round an Issue 3 board with a ZIF socket.
- ↑ Ferranti instructions and listings for the ULA 6C001 test tape, 30 September 1983, Ferranti Archives 2026 (SPEC-FER-COD-154). Source for the functional test sequence.
- ↑ Ferranti memo "Spectum Iss.6A memory timing", 7 November 1984, Ferranti Archives 2026 (SPEC-FER-MEM-044). Source for the Issue 6A board that failed with faster Mk 7 ULAs.