Sinclair ZX Spectrum Memory Timing

Ferranti's photographs of RAS (top), A0 and CAS on an Issue 2 board with a 6C001-6 ULA that "fails cold": below 0 °C, at about 70 °C, and with 150 pF added on CAS (10 August 1983)

Sinclair ZX Spectrum memory timing is the timing between the Sinclair ZX Spectrum ULA, the Z80A and the dynamic RAM of the 16K and 48K Sinclair ZX Spectrum. The lower 16K of RAM is shared between the ULA, which reads the display from it, and the processor, so the ULA's RAS and CAS strobes, the address multiplexers and the RAM's own limits all have to fit together. Ferranti's files of 1981 to 1984, released as the Ferranti Archives 2026, record how that fit was designed, how it went wrong in production at Timex in Dundee in 1983, and what was changed on the ULA and on the boards. Sinclair's service manual records the board side of the same changes.

These are period factory documents about manufacturing problems. They explain faults a repairer may meet and parts that may be found on a board, but they do not mean that every Spectrum has these faults. A memory fault on a Spectrum today still calls for the RAM to be checked first; see the last section.

How the memory is arranged

Sinclair's service manual describes the arrangement:

• Lower 16K (addresses 4000 to 7FFF): eight 16K by 1 dynamic RAMs, IC6 to IC13, type 4116 at 150 ns, organised as 128 rows by 128 columns. The ULA drives RAS, CAS, the write enable and its own seven address lines directly. The CPU's addresses reach the RAM through the 74LS157 multiplexers IC3 and IC4 and the series resistors R17 to R23, so that where both drive the address lines the ULA wins; R1 to R8 do the same on the data bus. The multiplexers select the low address bits as the row address while the ULA's RAS output is high, and switch to the high bits when RAS goes low. When the CPU wants this RAM while the ULA is fetching the display, the ULA stops the CPU clock.
• Upper 32K (8000 to FFFF, 48K models only): eight parts sold as 32K by 1 (TI 4532 or OKI MSM3732), which are 64K devices with one half not working; links select the maker and the working half. They have their own multiplexers (IC25, IC26) and their RAS, CAS and write timing comes from IC23 (74LS32) and IC24 (74LS00) with two RC delays.
• Refresh: the Z80's built-in refresh "only applies to the optional 32k expansion RAM". The lower 16K is refreshed "during normal read cycles": most rows each time the ULA reads the display, the rest by other reads that occur regularly.

From the Issue 5 board, and on Issue 6A, a single chip (IC27) replaces the TTL multiplexers and the upper-RAM timing logic; Sinclair's supplement calls it the "Mullard ZX 84/01" and Timex's drawing calls it the ZX8401.

The ULA's display fetch

The fetch was already drawn on the timing sheet "ZX81C-2" of 10 November 1981: one RAS, then two CAS cycles in page mode, the first reading the bitmap byte into a latch (DLATCH) and the second the attribute byte (ALATCH). Read from the sheet, the design called for RAS low for at least 200 ns, each CAS low for at least 150 ns with at least 65 ns between them, and RAS precharge of at least 80 ns, with "typically 75pF loading on RAS, CAS" and 35 pF on the address lines. The 5C102 timing diagrams of January 1982 show two such RAS cycles in every 16-pixel window, with a shift-register load (SLOAD) for each eight pixels. Outside the display the ULA's address and RAS outputs go to high impedance; the November 1981 design sheet notes "This allows refresh during non-active portion of frame".

Two undated Ferranti sheets set the fetch against the RAM's limits. One is a hand-lettered "Typical system timing (internal memory request)" diagram with a printed dynamic RAM table pasted beneath it; the other is a page of pencil notes on the 4116 and the 74LS157:

Dynamic RAM limits on Ferranti's timing sheets

Parameter	Value on the sheet	Sheet
tRCD, RAS to CAS delay	20 ns min, 50 ns max	SPEC-FER-SCH-051
tCAC, CAS to data valid	100 ns	SPEC-FER-SCH-051
tASR, row address set-up to RAS	0 ns min	SPEC-FER-SCH-051
tASC, column address set-up to CAS	−10 ns min	SPEC-FER-SCH-051
tRAH, row address hold from RAS	20 ns min (20 ns for the NEC 4116 in the pencil notes)	Both
tCAH, column address hold from CAS	45 ns min	SPEC-FER-SCH-051
tCP, CAS precharge in page mode	60 ns min	SPEC-FER-SCH-051
tRP, RAS precharge	100 ns min	SPEC-FER-SCH-051
Page-mode cycle drawn for the 4116 (150 ns)	RAS low 450 ns; each CAS low 200 ns; CAS high 70 to 90 ns between; RAS to CAS 40 to 42 ns	SPEC-FER-NOT-052
74LS157 select to output	National 16 ns typical, 23 ns max (low to high), 15 ns typical, 27 ns max (high to low); Signetics 23 and 27 ns max; Texas Instruments 74S157 8 ns and 74ALS157 6.5 ns	SPEC-FER-NOT-052

The multiplexer's select-to-output delay matters because the 74LS157s switch from row to column address when RAS falls, and the RAM needs the row address held for at least 20 ns after RAS. The pencil notes compare the makers' figures for exactly this.

R57 and the refresh problem of early 1983

Where R57 is

On Sinclair's Issue Two circuit diagram of 16 August 1982, R57 runs from the Z80's RFSH output (pin 28) to the RAS line of the lower RAM at IC6 pin 4 (read from the drawing). Ferranti's memo of early 1983 draws the same arrangement: the ULA's RAS output (pin 35) goes directly to the 4116s and through R32 (100 Ω) to the two 74LS157s, and the Z80's RFSH reaches the RAM RAS line through R57, drawn as 300 Ω. ITT's drawing gives 330 Ω, with 470 pF to ground on the RFSH side. The idea, as Ferranti understood it, was that during each Z80 refresh cycle the ULA lets its RAS output float and RFSH pulls RAS low through R57, so that the Z80's refresh address is strobed into the RAMs.

Sinclair's service manual settles which boards have it. Its parts list gives R57 as 330R on Issue 2 and not fitted on Issue 3, and the supplement lists it as "not used" on Issues 4A, 4B, 5 and 6A. Its list of Issue 1 modifications says that where the RAMs are of National manufacture, "R57 (330R) must be removed", with other changes. Timex's Issue 3 drawing of June 1983 has no resistor at that point on the RAS line (read from the drawing). So R57 belongs to Issue 1 and Issue 2 boards, and on those it may have been removed in the factory.

The same Issue 1 modification list has two related parts: a 100 pF capacitor from RAS to ground, "necessary only when using ULA 5C102", and a 470 pF capacitor from Z80 pin 28 to ground, "required only when IC2 and RAM ICs are all of NEC manufacture". The parts list also gives C54 as 470 pF on Issue 2 boards only, without saying where it sits. An undated Ferranti note records one board's state as "R57 in / C54 out", "100pF RAS out" and "Clock mod in": boards of the time were seen in different combinations.

What went wrong

In January 1983 Spectrums at Timex were corrupting memory. ITT, then supplying 4116 RAMs, described the problem in a memo of 27 January 1983: "When program executes, the memory is corrupted giving spurious characters on the screen and leading to program crash." ITT found every signal at the RAMs fairly clean except RAS, which rose only to about 3.5 V where the other clocks reached 4 to 4.5 V, and had a poor edge. Because the RFSH pulse is much wider than the intended RAS pulse, the RFSH line pulled RAS down earlier than intended, and ITT thought the poor edge was mis-clocking the row address. It listed six possible fixes:

ITT's six candidate fixes, 27 January 1983

No.	Fix	ITT's comment, and Ferranti's marks on its copy
1	A TTL gate on the ULA's RAS output	Gave the drive needed, but ITT had not known that the ULA's output goes to high impedance, so RFSH no longer worked
2	Remove R57	"It is not known whether some RAM row addresses are refreshed with this resistor removal"
3	An emitter-follower buffer on the ULA's RAS output	A trade-off in the emitter resistor, which must be much more than 330 Ω for RFSH to hold RAS high. Ferranti marked it with a question mark and a cross
4	A gate buffering RAS just before the RAM inputs, allowing a larger resistor in place of R57 (drawn as 680 Ω)	Ferranti wrote "extra delay" against the gate
5	Gate MREQ with RFSH in a 7432 (drawn with 470 Ω gating and 82 Ω into the RAM RAS), using the other gates to buffer RAS and add about 30 ns	A buffer is needed: "a buffer before the RAS inputs to the 4116 is essential to clean up the waveform"
6	Delay MREQ into the ULA with 470 Ω in series and 22 pF to ground	ITT thought this would let the system work although RAS would still have a poor edge. Ferranti put a question mark by it

Ferranti's report of a meeting at Timex on 2 February 1983 adds that ITT would guarantee its RAMs only to the 2 ms maximum refresh time, not to the 8 ms that results with R57 removed ("the same for all other suppliers incidentally"), and that Timex hoped fix six, the simplest, would "do the trick". The ITT engineer "fully supports our feeling that it is a system design fault and not a ULA reliability problem", suggested that batch variation in the Z80's RFSH could be part of it, and looked surprised to hear that ULAs which failed in one board worked in another. On 11 February 1983 Sinclair, Timex and Ferranti met; the agenda notes 48 Spectrum 5C112 rejects at Dundee. The documents do not show whether any of ITT's six fixes went into production.

Ferranti's tests

The 48 rejects were 5C112-2 ULAs with the date code 8301, out of a sample of 135 taken at Timex's incoming inspection. Ferranti's tests on a Spectrum board and on its Membrain tester failed five of them outright. Of the other 43, five more failed only with R57 fitted. Timex said it had tested the batch with R57 removed. Ferranti then ran all 43 again on an Issue 2 board with R57 out, each loading and running a program for at least five minutes: one had a dead Symbol Shift, one crashed once and not again, one had a noisy speaker and one poor colours, and the rest worked. The bench notes of 22 February 1983 log the soak test (games such as "Invaders", "Horace" and "Kong", 5 to 25 minutes per chip) and a list of nine chips that failed with R57 fitted:

5C112-2 returns with and without R57 (Ferranti notes, 22 February 1983)

Chip	With R57 fitted	With R57 removed
1	Won't load, garbage on screen when loading	OK
2	Won't load, garbage on screen when loading	OK
3	Garbage at switch-on	OK
4	Garbage at switch-on	Washed-out colours
5	Program crash	Program crash
6	Garbage at switch-on	Loaded garbage
7	Won't load	"GOSOL" (as written; not explained)
8	Garbage at switch-on	"GOSOSO" (as written; not explained)
9	"GOSOSO" (as written)	OK

The notes sum up "28 tested, 9 failed (48 total rec[eived])", tested with Timex's program on an Issue 2 board. Ferranti's memo on the same returns explains what it found:

• With R57 fitted, the Z80's RFSH goes low before the ULA's RAS output goes to high impedance, so RAS falls with a step; the Z80 drives about 100 pF of RAM input through R57, so the edges are slow; and during some refresh sequences the ULA holds RAS high instead of floating it, so the line sits at about 2.5 V. The 4116's minimum high input level on RAS is 2.7 V.
• With a variable resistor in place of R57, every sampled 5C112-2 return failed when the RAS high level was pulled down to 2.3 to 2.5 V (just under 300 Ω). Three older 5C112-1 chips, date code 8234, worked with it below 2.0 V.
• The returns' on-chip resistors were high: an equivalent input resistance averaging 20.6 kΩ, against 16.5 kΩ on the 5C112-1s and a nominal 16K ±30 per cent (20.8 kΩ maximum). That means weaker drive.
• With R57 disconnected, a diode clamp on RAS showed the RAMs actually worked down to about 2.0 V, the same with either batch, so the low level alone did not explain the failures.
• The memo's "highly probable" cause, not proven, was RAS precharge. At the end of an op-code fetch RAS rises slowly towards 2.5 V and is driven low again almost at once; the 4116-15 needs 100 ns of RAS precharge at 2.7 V, and with the 5C112-2s the pulse at the 2.0 V level was barely 100 ns wide.
• On the multiplexed address lines (the 74LS157 path) the 5C112-2s gave high levels below 2.3 V, against the RAM's 2.4 V minimum. The memo also notes reports that "some ULA's will function with RAM's from one manufacturer but not another".

Sinclair's recommendation was to leave R57 out. The RAMs are then refreshed only by the ULA's display reads, every 8 ms by the memo's account, which it calls well outside the specification, adding that "the memory suppliers are obviously unhappy about this situation". Samples of 6C material, with a 100 Ω totem-pole pull-up against 200 Ω on the 5C, gave much cleaner RAS; whether the 6C001 would stay in specification "needs to be investigated - by FERRANTI or SINCLAIR?". The memo ends by asking for a directive on whether R57 should be in or out on Ferranti's own TV test boxes, which were a mixture.

Timex's timing budget for the upper 32K (May 1983)

With its letter of 24 May 1983 Timex sent Ferranti a RAS and CAS timing chain for the upper 32K RAM (4532 type), as figure C:

• MREQ to RAS: one gate, 3 to 15 ns.
• RAS to the switch-over of the 74LS157 select (S2 in the figure): an RC delay (RC1) plus 3 to 15 ns. The 4532 needs at least 25 ns here.
• S2 to a valid column address: 16 to 27 ns for the 74LS157; the column address must be valid before CAS.
• S2 to CAS: a second RC delay (RC2) plus 3 to 15 ns. RAS to CAS must be 30 to 90 ns by the 4532 specification.
• CAS to data valid: 110 ns maximum for the -200 part, 160 ns for the -250. The Z80 allows 520 ns from MREQ to valid data.

Timex worked out that RC1 must be at least 22 ns and RC2 at least 24 ns, with the two together under 60 ns, and chose RC1 of 29 ns and RC2 of 31 ns at most. The boards carry two such RC networks in the upper-RAM logic: R70 (220R) with C64 (100 pF) and R71 (220R) with C63 (47 pF) on Timex's Issue 3 drawing, and the same values on Sinclair's plug-in 32K board.

The 32K memory board

Sinclair's manual says that on the Issue 1 board the 32K extension was a subsidiary board plugged into special DIL connectors, with TI 4532-3 or 4532-4 RAMs, all of one type; from Issue 2 the extra RAM went on the main board, with a link giving 0 V to select the -3 parts and +5 V for the -4. Ferranti's file holds full-size layout sketches, a connection list, photocopies of a real board and a pencil circuit of the plug-in board, marked "RAM 32 Issue 1" and © 1982:

• eight TMS4532-20NL4 RAMs, two 74LS157 multiplexers, a 74LS32 and a 74LS00, 0.047 µF decoupling per RAM, and RC delays of 220R with 100 pF and 220R with 47 pF;
• two 16-way sockets carrying A0 to A15, D0 to D7, MREQ, RD, WR, +5 V and 0 V only, with no ULA signals and no +12 V or −5 V;
• one multiplexer input tied to +5 V, paired with A10.

The layout sketches are on Ferranti Wythenshawe sketch forms; the file does not say why Ferranti drew the board.

Cold and warm failures and the mark 7 ULA (1983)

The later 1983 documents concern the timing of RAS, the address lines and CAS on 6C001 ULAs. An undated set of Ferranti Polaroids compares RAS and CAS on 6C001-5 ULAs with a 5C112-3: one 6C001-5 is labelled "crashes cold", another "memory fail when warm". On 10 August 1983 Ferranti photographed RAS, A0 and CAS on 6C001-6 samples from material marked "Low R (3.8K)", in Issue 2 and Issue 3 boards. Sample 4 "fails cold", and its traces were recorded at a case temperature at or below 0 °C, at about 70 °C, and with 150 pF added on CAS. The documents do not explain the "Low R" label.

The 6C001 logic diagram, issue 3, marked up for the mark 7: two inverters added in the address-select line and four in the CAS line

Six weeks later, on 23 September 1983, Ferranti asked Sinclair to confirm two changes to the 6C001: four inverters in the N.CAS line, adding typically 22 ns at 25 °C, and two in ADSEL, the line that switches the ULA's own address outputs from row to column address, adding typically 11 ns; worst case, the delays could be 1.7 times those figures. Sinclair agreed on 29 September 1983. Issue 2 of the logic diagram (14 February 1983) already has an "EXTRA DELAY" box pencilled into ADSEL, and issue 3 (10 October 1983) has the gates drawn in, marked on one print "added on MK7". The documents do not state the reasoning in words, but the sequence is fast Mark 6 parts failing cold in August and delay added to CAS and address select in September. The NTSC 6C011 was brought to the same timing in 1984.

The boards changed too. From Issue 4A, Sinclair's supplement says, R32 was deleted and "two spare gates from IC24 have been used to improve ULA timing", in series between the ULA's RAS output and the display RAM multiplexers, and "it is important that ULA 6C001-7 or later issues" are used. On Issue 5 an inverter chip, IC28, "is used in the decoupling of the RAS/CAS function".

Issue 6A and the ZX8401 gate array (1984)

Sinclair's specification for the ZX8401, revision 3 of April 1984, describes a 40-pin chip that "performs the functions of display address multiplexer, 32k dRAM address multiplexer and 32k dRAM timing generator for the ZX Spectrum personal computer". Timex's Issue 6A drawing of 25 September 1984 ("Ferranti version") shows it as IC27 in place of the 74LS157s, with a 74LS04 (IC28) whose inverters sit in pairs in the timing lines between link points marked C in, C out, R in and R out, and a 180 pF capacitor (C105) on the ZX8401's CAS output.

ZX8401 pin-out (Sinclair specification, revision 3)

Pin	Signal	Pin	Signal	Pin	Signal	Pin	Signal
1	DRASL	11	A3	21	A6	31	MA2
2	A0	12	A10	22	A13	32	MA1
3	A7	13	DMA3	23	DMA6	33	MA0
4	DMA0	14	A4	24	TS1	34	CASL
5	A1	15	A11	25	TS2	35	MREQDL
6	A8	16	DMA4	26	MA7	36	MREQL
7	DMA1	17	A5	27	MA6	37	A15
8	A2	18	A12	28	MA5	38	RDL
9	A9	19	DMA5	29	MA4	39	WRL
10	DMA2	20	VSS (0 V)	30	MA3	40	VDD (+5 V)

DMA0 to DMA6 are the multiplexed addresses for the lower 16K, which reach the RAM through series resistors with the Ferranti ULA on the other side; MA0 to MA7 address the upper 32K; TS1 and TS2 select the RAM type; CASL is the upper RAM's CAS. The specification asks for VDD of 5 V ±5% and 0 to 70 °C, and gives these timings among others:

• address change to multiplexed address change, 50 ns maximum; MREQL to multiplexed address, 80 ns maximum; WRL, RDL or A15 to CASL, 120 ns maximum;
• multiplexed address change to CASL low, 5 ns minimum and 35 ns maximum;
• TCAR 60 ns maximum and TRAH 20 ns minimum, with the series resistor RC 330 Ω ±5%, RP 680 Ω ±5% and the load CL between 25 and 60 pF; "An optional external delay using LS04 inverters and an R-C network may be used to help achieve the minimum timing spec";
• a load on CASL of 25 to 100 pF, always more than on any MA line. Beside this line on the archive copy someone has written "180pF in circuit".

The specification's series resistor is 330 Ω; Sinclair's parts list and Timex's Issue 6A drawing give R17 to R23 as 470R on the Issue 5 and 6A boards.

Ferranti's study of three gate arrays (November 1984)

In November 1984 Ferranti examined three Issue 6A boards, each with a new gate array from a different maker, against an Issue 3 board with TTL multiplexers. The memo describes the gate array as replacing IC3, IC4 and IC23 to IC26 to generate the row and column addresses for both RAMs, which is the job of the ZX8401. The same 6C001 Mk 7 ULA was used on every board, and RAS, A0 and CAS were photographed on each.

Issue 6A gate arrays compared with TTL (Ferranti memo, 7 November 1984)

Board	Gate array marking	Result
A	Issue 3, TTL logic	Reference
B	Texas Instruments CF70001	Virtually identical to the TTL logic
C	Signetics PCF1306P	About 20 ns slower
D	"fela", attributed in the memo to "Norsem?"	Over 30 ns slower. Worked with the ULA used for the tests, but failed with other Mk 7 ULAs about 10 ns faster

The memo's findings:

• The critical figure appeared to be the column address set-up time to CAS, tsu(CA). Sinclair had specified 5 ns minimum; Texas Instruments specifies −5 ns minimum for its 4164.
• The positive-going edge on A0 about 50 ns after RAS falls comes from the ULA and is the same on every board; the other transitions come from the gate array.
• All three 6A boards had the 74LS04's two-gate delay linked into the address-select line, which makes tsu(CA) worse; the links could put it in the address-select or the CAS line. Removing it gained about 10 ns on the "fela" board, which the author still thought could give problems.
• The 32K RAM's address timing "looked quite poor on all boards, but especially so on the NORSEM one", and a 180 pF capacitor hung on its CAS line, presumably to add delay, was "poor design practise".
• Only one sample of each was examined, and only at room temperature, so the results are only an approximate guide.

Sinclair's supplement names the Issue 5 and 6A chip as the "Mullard ZX 84/01". So a 6A board may carry any of several makes of IC27, and in Ferranti's tests they did not have the same timing.

What this means when repairing a Spectrum

The archive does not change the usual order of work on a Spectrum with memory faults. It adds reasons why a board can misbehave with parts that each test good.

• Check the RAM first. Sinclair's own procedure for a machine that does not initialise changes the lower RAMs from IC13 down to IC6 before the ULA and then the Z80. See Sinclair ZX Spectrum Troubleshooting Guide.
• Then consider timing. If the RAM tests good and faults remain, especially garbage on the screen, crashes or failure to load, the ULA-to-RAM timing is a candidate. Those were the symptoms recorded on the 1983 rejects.
• Note whether the fault depends on temperature. Ferranti's 1983 notes record ULAs that crashed only cold and others with memory failures only when warm, and photographed timing below 0 °C and at about 70 °C. Sinclair's supplement says to test "at elevated temperature to show up faults" in picture quality and RAM, and the Thorn EMI servicing manual's repair data blames the heatsink and then the ULA for faults that appear only when warm.
• Expect mixed makes to interact. The documents record ULAs that worked with one RAM maker's chips and not another's, board modifications that depend on the RAM and Z80 maker, ULAs that failed in one board and worked in another, and Issue 6A gate arrays whose timing differed by over 30 ns. A replacement ULA, RAM or IC27 of a different make or mark can therefore cure or cause a fault. Fit the mark the board was built for where possible; from Issue 4A that means 6C001-7 or later.
• Measure what Ferranti measured. It compared RAS, A0 and CAS on three channels at 10 ns per division. On Issue 6A boards the A0 edge about 50 ns after RAS falls comes from the ULA and can be ignored. On Issue 1 and 2 boards look at the RAS high level and edges during refresh as well.

Parts a repairer may find on early boards, and what the documents say about them:

Factory modifications and possible bodges around the memory timing

Part	Boards	What the documents say
R57, 330R from Z80 RFSH (pin 28) to the lower RAM's RAS	Issue 1 and Issue 2	Fitted on Issue 2 in Sinclair's parts list, not fitted from Issue 3. Removed on Issue 1 boards with National RAMs, and Sinclair recommended leaving it out in early 1983. Its absence from an early board can be a factory decision
100 pF from RAS to ground	Issue 1	"Necessary only when using ULA 5C102"
470 pF from Z80 pin 28 to ground	Issue 1	"Required only when IC2 and RAM ICs are all of NEC manufacture"; not required where R57 is removed for National RAMs
C54, 470 pF	Issue 2 only	Position not given in the manual; Sinclair's fault list says "Random dynamic squares: change C54"
74LS00 on a small board wired to Z80 pins 4, 5 and 20 and ULA pins 36 and 37	Issue 1 and early Issue 2 with the 5C102	Factory "spider" modification for the 5C102's timing fault, about 40,000 units
Transistor (TR6) or diode and resistor from Z80 A0 to ULA IORQ (pin 33)	Issue 2 with the 5C112; TR6 is on the layout from Issue 3	Factory modification for the 5C112
A TTL buffer on RAS, 470 Ω and 22 pF on MREQ into the ULA, or a 7432 gating MREQ with RFSH	Early boards, if anywhere	ITT's candidate fixes of January 1983. The documents do not show that any was used in production
Two gates of IC24 in series with the ULA's RAS output; R32 deleted	Issue 4A onwards	Factory change; needs a 6C001-7 or later
74LS04 (IC28) with link points C in, C out, R in and R out	Issue 6A	Puts a two-gate delay in the address-select or CAS line. In Ferranti's November 1984 study all three boards had it in the address-select line, which made the set-up time worse
180 pF (C105) on the ZX8401's CAS output	Issue 6A	Outside the 25 to 100 pF in the ZX8401 specification; Ferranti called it "poor design practise"

Related pages

• Sinclair ZX Spectrum ULA
• Sinclair ZX Spectrum
• Sinclair ZX Spectrum Troubleshooting Guide
• Sinclair ZX Spectrum General Maintenance
• Sinclair ZX Spectrum Service Manual
• ZX Spectrum Servicing Manual (Thorn EMI Datatech, 1984)
• Ferranti Spectrum ULA Test Box
• Ferranti Archives 2026: the collection of Ferranti files, with every scan in Category:Ferranti Archives 2026